Full digital calibration module for TIADC (Time-Interleaved Analog-to-Digital Converter) sampling time error and calibration method thereof

Abstract

The invention discloses a full digital calibration module for a TIADC (Time-Interleaved Analog-to-Digital Converter) sampling time error. A TIADC consists of a clock module, a data conversion module,a calibration module and a data compounding module, wherein the calibration module comprises a symbol judgment unit, a high-order time error compensation unit and an error extraction unit. Through adoption of the full digital calibration module, TIADC system calibration suitable for any channel can be finished with relatively low hardware consumption. Moreover, the calibration scheme can be used for calibrating a signal within the entire Nyquist sampling frequency and performing efficient compensation, so that the calibration of a time error between channels can be realized quickly and accurately with relatively low hardware overhead.

Description

technical field [0001] The invention relates to the field of analog-to-digital conversion, in particular to an all-digital calibration module for sampling time error of a multi-channel time-interleaved analog-to-digital converter and a calibration algorithm thereof. Background technique [0002] With the rapid development of social information technology, the performance requirements of analog-to-digital converters (Analog-to-digital) in the fields of communication, computer, and instrument control are getting higher and higher, so high-performance ADCs have a very wide range of applications, and has important strategic significance. Limited by the current level of ADC development and technology, the performance of a single ADC is difficult to meet the requirements of high speed and high precision at the same time, so the time-interleaved analog-to-digital converter (TIADC) came into being. [0003] TIADC (Time-Interleaved Analog-to-Digital Converter) is a parallel alternat...

AI Technical Summary

Problems solved by technology

Limited by the current level of ADC development and technology, the performance of a single ADC is difficult to meet the requirements of high speed and high precision at the same time, so the time-interleaved analog-to-digital converter (TIADC) came into being

[0003] TIADC (Time-Interleaved Analog-to-Digital Converter) is a parallel alternating ADC. The parallel structure can greatly improve the sampling rate of the system, but due to the time mismatch and gain of each channel Mismatch and offset mismatch, three kinds of mismatch seriously affect the performance of TIADC

At present, TIADC has two main calibration schemes for sampling time errors: the foreground calibration algorithm based on known input signals and the background calibration algorithm based on unknown input signals. The foreground calibration algorithm has the advantages of low hardware complexity and high calibration accuracy, but it needs to be interrupted. The work of the ADC does not have the ability to calibrate the error in real time, and the background calibration algorithm can accurately calibrate the error in real time

In the background calibration algorithm, there are time error detection schemes based on polarity, frequency domain and correlation, and time error compensation schemes are mainly based on Taylor, Farror and variable delay line schemes, but most of the calibration schemes have the following One or more of the problems: high hardware complexity, too small input bandwidth, inability to calibrate multi-frequency signals, not full digital calibration, low calibration accuracy, etc.

The literature [TAILER SERIES-BASED TIADC CHANNEL ERROR ADAPTIVE CORRECTION METHOD, WANG Yajun] proposes a correction scheme based on the reference channel, but the additional reference ADC increases the hardware consumption of the system, and the literature [An8Bits4Gs / s120mWCOMSADC, HegongWei] proposes a An error extraction scheme based on statistics, which can extract the time error simply and effectively, however, this scheme uses a variable delay line to compensate the time error, which leads to low calibration accuracy. The literature [A TIADC time mismatch error self- Adapt to the calibration algorithm, Yin Yongsheng] proposed a compensation scheme based on the first-order Taylor cascade, this scheme has high calibration accuracy, but it cannot handle multi-frequency signals, the literature [Research and Design of Time-Interleaved ADC Full Digital Calibration Algorithm, Jian Maochen ] proposed a compensation scheme based on high-order Taylor, which has high calibration accuracy and can effectively calibrate signals within the Nyquist sampling frequency, but it uses an equal-ripple best approximation bandpass filter, which not only consumes a lot of hardware resources , and there is still the problem of inaccurate judgment

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