Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps of forming a substrate, wherein the substrate comprises a substrate, a gate structure located on the substrate, source-drain doped regions located in the substrate at two sides of the gate structure, and a dielectric layer located on the substrate from which the gate structure is exposed;forming contact openings for exposing the source-drain doped regions in two sides of the gate structure, wherein each contact opening comprises a through hole penetrating through the substrate with the thickness of the dielectric layer, and a groove penetrating through the substrate with the thickness of the part corresponding to each source-drain doped region, and the bottom size of each grooveis smaller than the top size in the direction vertical to the extension direction of the gate structure; covering the surfaces of the grooves with a metal silicide layer in a conformal manner; and forming the metal silicide layer and then forming contact hole plugs in the contact openings. The bottom size of each groove is smaller than the top size, so that, compared with a scheme that side wallsof the grooves are vertical to the substrate, the semiconductor structure has the advantages that the diffusion distance from metal atoms to a channel region in the process of forming the metal silicide layer can be increased, and the possibility that the metal atoms are diffused to a bulk region of the substrate is reduced, thereby reducing bulk leakage current.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes the surface of the wafer unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of the interconnection line after the critical dimension is reduced, at present, the conduction between different metal layers or between the metal layer and the substrate is realized through the interconnection structure. The interconnection structure includes interconnectio...

AI Technical Summary

Problems solved by technology

[0006] However, the electrical performance of the formed semiconductor device still needs to be improved after adopting the metal silicide layer technology.

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