Uniform de-layering method for aluminum process chip

Abstract

The invention discloses a uniform de-layering method for an aluminum process chip. The method comprises: acquiring layer thickness information, including the thickness of a metal wiring layer, the thickness of a dielectric via hole layer and the thickness of the barrier layer, of a chip; according to the layer thickness information and an etching rate, determining first etching time and etching afirst barrier layer being one barrier layer arranged at the outer surface side of the metal wiring layer in preset etching gas; removing the metal wiring layer by using rubber; and etching a second barrier layer being one barrier layer arranged at the inner surface side of the metal wiring layer in etching gas. According to the method disclosed by the invention, the rubber is used as a tool for removing the metal wiring layer and the aluminum can be etched selectively, so that a via hole phenomenon and an edge effect are avoided.

Description

technical field [0001] The invention relates to the technical field of chip failure analysis, in particular to a uniform delamination method for aluminum process chips. Background technique [0002] The chip is composed of a multi-layer metal wiring structure and a dielectric via layer structure, and the metal wiring layer has the same three-layer structure, such as figure 1 As shown, where M1-M6 represent six layers respectively, M1 is the first layer closest to the machine layer, and so on. When the chip fails internally, it is necessary to delaminate the chip layer by layer to analyze the cause of failure; and when analyzing the details of the chip circuit, it is also necessary to delaminate the chip layer by layer to observe the internal structure of the chip. Chip delamination refers to the smooth removal of the metal layer of the chip and the dielectric via layer (or passivation layer) on the metal layer. The failure analysis field needs to ensure the flatness of the ...

AI Technical Summary

Problems solved by technology

Dropped holes will cause the engineer to be unable to effectively judge the connection relationship between the metal lines when extracting the circuit, which will affect the judgment of the circuit function

The problem of edge effect is that in the process of using CMP to grind and polish the barrier layer, the edge grinding and polishing speed is always greater than the middle grinding and polishing speed, so the layer-by-layer transfer phenomenon will be caused during

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