Thin film transistor, preparation method thereof, array substrate and display device
A technology of thin film transistors and substrate substrates, which is applied in the direction of transistors, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of cumbersome preparation process and high preparation cost of thin-film transistors, and achieve the goal of reducing the difficulty of process preparation and reducing the preparation cost Effect
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[0043] Based on the same inventive concept, the embodiment of the present invention also provides a method for preparing a thin film transistor, such as figure 2 As shown, the following steps may be included:
[0044] S201, forming a pattern of an active layer on a base substrate; wherein, the active layer includes a metal oxide semiconductor material;
[0045] S202. Using a plasma-enhanced chemical vapor deposition process to form a pattern of at least two sub-etch stopper layers stacked over the active layer and via holes penetrating through each sub-etch stopper layer on the active layer, so as to form Etching barrier layers and doping metal oxide semiconductor materials with oxygen ions and hydrogen ions;
[0046] S203 , forming source and drain electrodes electrically connected to the active layer through via holes penetrating through the etch barrier layer on the etch barrier layer.
[0047] In the manufacturing method of the thin film transistor provided by the embod...
Embodiment 1
[0070] to prepare figure 1 The structure shown is taken as an example, and the method for preparing a thin film transistor provided in the embodiment of the present invention may include the following steps:
[0071] (1) A gate pattern is formed on a base substrate.
[0072] Specifically, a patterning process is used to form the pattern of the gate 140 on the base substrate 100, such as Figure 3a shown. Wherein, the material of the gate may include Cu.
[0073] (2) Form the pattern of the gate insulating layer 150 covering the gate 140 on the base substrate 100 formed with the gate 140, such as Figure 3b shown.
[0074] Specifically, the gate insulating layer may include two sub-gate insulating layers. Patterns of two layers of sub-gate insulating layers covering the gate are formed on the base substrate on which the gate is formed by using one patterning process respectively.
[0075] (3) A pattern of the active layer is formed on the base substrate on which the gate ...
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