Flash memory

Abstract

The invention discloses a flash memory; in a flash memory unit array, a semiconductor substrate surface comprises active regions isolated by field oxide layers; the active regions are arranged in parallel in a bar-shaped structure; a polysilicon floating gate is located on the top of the active region and isolated by a first gate oxide layer; in the width direction of the active region, when the side face of the polysilicon floating gate and a corresponding active region side face are under a lithography alignment condition, the width expansion of the polysilicon floating gate can be formed byetching consumption of the field oxide layer; two side faces of each polysilicon floating gate are provided with convex-concave structures; the convex portion and concave portion of the convex-concave structure are mutually matched in positions, thus expanding the side face spacing of the polysilicon floating gate. The mutual interferences between adjacent polysilicon floating gates can be reduced, thus increasing drain electrode voltage, improving the programming speed, increasing the coupling rate between a control gate and the floating gate, further reducing the grid voltage, and further reducing the flash memory sizes.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit, in particular to a flash memory (Flash). Background technique [0002] Flash memory has been widely used as the optimal choice for non-volatile memory applications due to its high density, low price, and electrically programmable, erasable advantages. At present, the flash memory cell is mainly carried out at the 65nm technology node. With the requirement for high-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology node. The feature size of high-node technology is smaller, so it can improve the integration level of flash memory. At the same time, the increasing maturity of new technology nodes also promotes the production of flash memory cells at high nodes. [0003] In the existing process, in theory, the width side of the polysilicon floating gate is usually self-aligned with the edge of the active region, but in practic...

AI Technical Summary

Problems solved by technology

However, with the application of high-node technology, the situation that the width of the polysilicon floating gate is greater than the width of the active area will bring greater adverse effects, especially in the scaling down of the size, which usually affects the active area and field oxidation. The width of the layer is reduced proportionally, and the size of the pad oxide layer will not change, so the consumption of the field oxide layer caused by the etching of the pad oxide layer will change the size of the active region and occupy the width of the active region The ratio will gradually increase

The situation that the width of the polysilicon floating gate is greater than the width of the active region will make the spacing between the polysilicon floating gates smaller than the spacing between the active regions, and the reduction of the polysilicon floating gate spacing will increase the mutual interference between the polysilicon floating gates, Lead to stored information errors, and the pitch of polysilicon floating gates will decrease sharply as the size of technology nodes shrinks

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