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An ldpc decoder with configurable multi-code length and multi-code rate

A decoder and code length technology, applied in the field of communication, can solve the problem that the decoder cannot use multiple code lengths and multiple code rates at the same time, and the code rate is single and variable.

Active Publication Date: 2020-06-16
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantages of this decoder are, first of all, the variable node calculation unit and check node calculation unit used by the decoder only correspond to a check matrix structure, the code rate is single, and the requirements for different services , the decoder cannot meet the decoding requirements of coexistence of multiple code lengths and multiple code rates. Secondly, the decoder does not package the function of extracting parity check base matrix parameters into a fixed module. When the code length and code rate change Finally, the transplantation of the decoder is difficult. Third, the partial parallel structure adopted by the decoder only solves the problem that the decoder with a single code length and a single code rate can improve its throughput while taking into account low hardware resource consumption. , not suitable for decoders with multiple code lengths and multiple code rates
However, the weak point that the decoder still exists is that although the decoder realizes the variable code length, it does not realize the variable code rate.
Moreover, the decoder cannot simultaneously use multiple code lengths and multiple code rates in the same system

Method used

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  • An ldpc decoder with configurable multi-code length and multi-code rate
  • An ldpc decoder with configurable multi-code length and multi-code rate
  • An ldpc decoder with configurable multi-code length and multi-code rate

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Embodiment Construction

[0020] The present invention will be further described below in conjunction with the accompanying drawings.

[0021] refer to figure 1 , the decoder structure of the present invention is further described. The decoder structure includes a three-layer structure of a top-level module, a core decoding layer module, and a verification layer module. The overall structure of the decoder is divided into functions, and the top-level module It is used to complete the timing and flow control of the decoder in the decoding process; the core decoding layer structure is used to complete the core iterative decoding work of the decoder; the verification layer is used to complete the calculation of the verification information by the decoder Work with storage.

[0022] refer to figure 2 , to further describe the top-level structure of the present invention, the top-level module includes a storage input soft information unit, a storage output soft information unit, a storage checksum unit, ...

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Abstract

The invention discloses a low density parity check code (LDPC) decoder capable of configuring multiple code lengths and multiple code rates. The decoder includes a three-layer structure, wherein a toplayer module includes a storage input soft information unit, a storage output soft information unit, a storage checksum unit, a decoding control unit, a macro definition unit and a core decoding unit; a core decoding layer module includes an initialization unit, an iterative control unit, a variable information processing unit (VPU), a check information processing unit (CPU), an iterative information storage unit, a row logic connection unit, a column logic connection unit and a verification unit; and a verification layer module includes a verification core unit and a checksum calculation unit. The decoder can flexibly configure multiple code lengths and multiple code rates, can also improve the throughput of the decoder, and is suitable for decoding the LDPC with multiple code lengths and multiple code rates.

Description

technical field [0001] The present invention relates to the field of communication technology, and further relates to a configurable multi-code length and multi-code rate LDPC (Low Density Parity Check Code) decoder in the field of wireless communication technology. The present invention provides a low-density parity-check code LDPC decoder structure that can be configured with multiple code lengths and multiple code rates. The decoder under this structure has multiple code lengths and multiple code rates are compatible, and the code length code The feature that the rate can be flexibly configured can be applied to the decoding work of low-density parity-check code LDPC with various code lengths and various code rates. Background technique [0002] Low-density parity-check codes are a class of linear block codes with a sparse parity check matrix proposed in the 1960s. Its bit error performance is very close to the Shannon limit, and it has the characteristics of flexible st...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11H04L1/00
CPCH03M13/1111H03M13/1148H04L1/0057H04L1/0061
Inventor 马卓昶旭阳杜栓义张益嘉张伟龚威
Owner XIDIAN UNIV