Interrupt verification system based on interrupt control flow graph

A technology of control flow graph and verification system, applied in the direction of program control design, multi-programming device, instrument, etc., can solve the problems of affecting safety, complexity, interrupt data competition and lack of time property detection technology and method, etc. The effect of reliability and security

Active Publication Date: 2018-08-31
EAST CHINA NORMAL UNIV +1
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Problems solved by technology

However, there are usually a large number of different interrupt sources (sources that signal interrupt requests) in an interrupt driver, and even most real-time systems support nested interrupts in interrupt handlers, through which an interrupt can be assigned a higher priority These situations lead to the same randomness and complexity of the interrupt handler
In addition, due to the introduction of the interrupt mechanism, the interrupt driver will generate another data race that may affect security—that is, two threads access the same shared variable at the same time, and at least one of the two accesses is to the variable. write value
Therefore, in the embedded field, software errors caused by interrupts still often occur. However, the detection techniques and methods related to interrupt data race and time nature are still relatively lacking.

Method used

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  • Interrupt verification system based on interrupt control flow graph
  • Interrupt verification system based on interrupt control flow graph
  • Interrupt verification system based on interrupt control flow graph

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[0080] Such as image 3 , Figure 4 as shown, image 3 shows a structure of the main control flow graph, including the main control node, branch 1, branch 2, branch 3 and the directed edges between each node, Figure 4 shows a structure of interrupt processing control flow graph, including interrupt node, branch 1, branch 2, branch 3 and the directed edges between each node, set Figure 4 The interrupt handling control flow graph shown in image 3 The interrupt handler for the interruption of the master control flow graph, and each node is executed only once, then the worst path analysis process is:

[0081] 1) Merge the marked nodes in the same branch in the main control program into one node;

[0082] 2) Merge all marked nodes in the same branch in the same interrupt handler in the branch corresponding to the main control program of the appeal into one node.

[0083] Among them, ci represents the instruction cycle in the basic block i, and ni represents the number of ...

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Abstract

The invention discloses an interrupt verification system based on an interrupt control flow graph. The system comprises a code conversion module, an interrupt information statistical module, a controlflow graph generation module, an interrupt control flow graph generation module, a processing module and an analysis module, wherein the code conversion module is used for obtaining an assembly codeaccording to an interrupt driving program; the interrupt information statistical module carries out statistics of interrupt information according to the assembly code; the control flow graph generation module generates the control flow graph according to the assembly code; the interrupt control flow graph generation module generates the interrupt control flow graph according to the control flow graph and the interrupt information; the processing module is used for carrying out slicing processing on the interrupt control flow graph; and the analysis module verifies the time safety and the memory safety of the interrupt driving program according to an interrupt control flow graph slice. The invention puts forward a new a model-interrupt control flow graph used for showing the control flow structure of the interrupt driving program and gives a method for cutting off the scale (slice) of the interrupt control flow graph, two categories of problems which appear most often in the interrupt driving program are verified in the same model, and the verification reliability and safety of the interrupt driving program is improved.

Description

technical field [0001] The invention relates to the field of static analysis of computer codes, in particular to an interrupt verification system based on an interrupt control flow graph, which is used for verifying the time safety and memory safety of an interrupt driver. Background technique [0002] Today, with the rapid development of information technology and mobile Internet, the development of embedded real-time systems has also made remarkable progress, and is widely used in computer-related industries, such as: manufacturing, medical, transportation and communication industries. In addition, embedded real-time systems are widely used in key fields such as energy, aerospace, and military affairs. Therefore, once these systems make mistakes, it will cause immeasurable losses. Particularly important. In fact, the correctness and reliability of the real-time system work not only depends on the results produced by the system operation, but also depends on the time requi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48
CPCG06F9/4812
Inventor 史建琦佘庆黄滟鸿郭欣熊家文毛侠
Owner EAST CHINA NORMAL UNIV
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