A 14t anti-irradiation static storage unit

Abstract

The invention discloses a 14T anti-radiation static storage unit, which can improve the anti-SEU capability, greatly increase the unit speed and reduce power consumption under the condition of sacrificing a small unit area. In the read and write phase, the WL signal is high. When the circuit is in the write phase, if BL is high and BLB is low, then write '1' to the storage node Q through the differential input transistors N4 and N5; if BL is low, BLB is high , then write '0' to the storage node Q through the differential input transistors N4 and N5. When the circuit is in the read phase, both BL and BLB are high. If the data stored in the cell circuit is '1', then BLB discharges to the ground through transistors N4 and N0, causing a voltage difference on the bit line, and then passes through the sense amplifier. Read data; if the data stored in the unit circuit is '0', then BL discharges to the ground through transistors N5 and N1, so that a bit line voltage difference is generated, and then the data is read out through the sense amplifier.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a unit circuit structure capable of increasing the writing speed of a storage unit, reducing unit power consumption and improving the ability of the unit to resist Single Event Upset (abbreviated as SEU). It is a 14T Radiation-resistant static storage unit. Background technique [0002] With the reduction of feature size and power supply voltage, the circuit is more and more sensitive to radiation, and the single event effect (Single Event Effect, abbreviated as SEE) becomes an inevitable problem, which makes the development of SEE radiation resistance hardening technology in combinational circuits very urgent. . SEU is a form of SEE, which is a soft error and non-destructive. When heavy ion particles are incident on the semiconductor material, the excess charges will be ionized, and these excess charges will be collected by the electrodes of the device, resulting in er...

AI Technical Summary

Problems solved by technology

Compared with the traditional six-tube unit and Dual Interlocked Storage Cell (DICE) structure, it has better anti-SEU ability, but the unit has poor write margin and consumes a lot of power

[0004] 2) if figure 2 and image 3 The two NovelSort Error Hardened 10T SRAM Cells circuits proposed by In-Seok Jung and Yong-Bin Kim in 2012 are hardened NMOS stacked 10T SRAM cell (NS10T) and hardened PMOS stacked 10T SRAM cell (PS10T). structure, in which the NS10T circuit can only restore the flip from 0 to 1, and the PS10T can only restore the flip from 1 to 0, and both circuits can solve the problem of multi-node disturbance caused by charge sharing, but the two circuits Slow write speed and high power consumption

But this circuit has slow write speed and poor read ability

[0006] 4) if Figure 5 Shown is a Highly ReliableMemory Cell (RHD12T) circuit proposed by Chunhua Qi and Liyi Xiao in 2016. This circuit greatly enhances the anti-SEU ability of the circuit by using source isolation technology. It can not only improve the anti-SEU ability of a single node but also It can improve the ability to resist multi-node flipping, but the writing speed of this circuit is slow and the power consumption is large

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