14T radiation-proof SRAM (Static Random Access Memory) storage unit circuit

Abstract

The invention discloses a 14T radiation-proof SRAM (Static Random Access Memory) storage unit circuit, which comprises eight NMOS (N-channel Metal Oxide Semiconductor) transistors and six PMOS (P-channel Metal Oxide Semiconductor) transistors, the PMOS transistor P5 and the NMOS transistor N3 form a first inverter, the PMOS transistor P6 and the NMOS transistor N4 form a second inverter, and the two inverters are in cross coupling; the internal storage nodes QB and Q are reinforced by the N1 and the N2, and the Q and the QB are all surrounded by the NMOS transistors, so that a polarity reinforcing structure is formed; peripheral nodes S0 and S1 are cross-coupled by P1 and P2, and N5 and N6 are used as pull-down tubes; the QB and the Q are connected to the BLB and the BL through the N7 and the N8, and the grid electrode of the N7 and the grid electrode of the N8 are electrically connected with the word line WL. The single event upset resistance of the unit can be improved, all single-node upset can be resisted, peripheral storage double-node upset can also be resisted, the critical charge of the unit is relatively high, and the unit is more stable.

Description

technical field [0001] The invention relates to the technical field of SRAM (Static Random Access Memory, static random access memory in Chinese), in particular to a 14T (14T refers to 14 CMOS tubes) anti-irradiation SRAM storage unit circuit, which is a kind of anti-single The unit circuit structure of the single event upset (SEU) capability, hereinafter referred to as HRH-14T. Background technique [0002] With the rapid development of the integrated circuit industry, the process has been continuously reduced, and the industry's demand for circuit performance and operational reliability of devices has continued to increase. However, in cutting-edge technology fields such as aerospace and aerospace defense, the space environment is particularly complex. High-energy charged particles such as electrons and protons seriously threaten the stable operation of integrated circuits, which makes the normal operation of aerospace equipment face severe challenges. Among them, the sin...

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Problems solved by technology

Compared with the traditional six-tube unit structure, it has better anti-SEU ability, but the internal storage node of the unit can only recover from '1' to '0' flip after being bombarded by particles, and is not completely immune to SEU

[0005] (2) if figure 2 The circuit shown is a Quadruple Cross-Coupled Latch-Based QUCCE 10T (QUCCE 10T) circuit proposed by Jianwei Jiang in 2018. It uses 10 transistors to form a circuit with a small area, but it can only recover from '0' SEUs to '1', cannot restore all SEUs

[0006] (3) if image 3 The circuit shown is the WritabilityEnhanced QUATRO (We-QUATRO 12T) circuit proposed by L.D.T.Dand and J.S.Kim in 2017. This circuit adds a pair of read-write tubes to the QUATRO circuit to improve the writing ability, but it is different from the QUATRO Like -10T, not fully immune to SEU

[0007] (4) if Figure 4 The circuit shown is a PowerOptimized SRAM Cell With High Radiation Hardened (RHBD 14T) circuit proposed by Govind Prasad et al. Operating time is relatively poor

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