A kind of manufacturing method of high-voltage vdmos device
A manufacturing method and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of low impurity activation rate at annealing temperature, high forward voltage drop of device diode, and large diode loss, etc. Yield, the effect of reducing forward voltage drop and on-resistance, reducing contact resistance
Active Publication Date: 2021-10-15
江苏新顺微电子股份有限公司
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However, such a backside implantation process is performed after the front side process is completed. Since the front side metal has already been formed, the annealing after the backside implantation cannot use a process temperature condition exceeding the alloy temperature. Generally, the backside implantation annealing temperature is between 400°C and 450°C. , such annealing temperature impurity activation rate is very low, and the defects introduced by large-dose back implantation are not fully repaired, resulting in high forward voltage drop of device diode and high diode loss
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[0027] The implementation of the aluminum-free CVD Schottky diode chip and its manufacturing process proposed by the present invention will be further described below in conjunction with specific examples. And it should be noted that all the drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly illustrate the structure and implementation of the present invention.
[0028] see image 3 , the present invention relates to a kind of manufacturing method of high-voltage VDMOS device, mainly carry out back implantation before the front process, carry out doping to the back, and grow LPSiN (SiN 3 N 4 ) to protect the back of the wafer, and then perform the front process of the wafer, thereby increasing the doping concentration on the back, reducing the contact resistance, and obtaining lower device diode forward voltage drop and on-resistance. Specifically, it includes the following steps:
[0029] Such as Figure 4 As shown...
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Abstract
The invention relates to a method for manufacturing a high-voltage VDMOS device, which is characterized in that the method is performed by implanting the back side before the front side process, doping the back side, and growing Si 3 N 4 The back of the wafer is protected, and then the front of the wafer is processed, so as to increase the doping concentration on the back, reduce the contact resistance, and obtain lower device diode forward voltage drop and on-resistance.
Description
technical field [0001] The invention relates to a manufacturing method of a high-voltage VDMOS device. It belongs to the technical field of integrated circuit or discrete device manufacturing. Background technique [0002] In the manufacturing process of high-voltage VDMOS devices using antimony-doped substrates, the back contact resistance has always been an important factor affecting the forward voltage drop and on-resistance of device diodes. Since the doping concentration of the antimony-doped substrate is not high enough, the general substrate resistivity is 0.008-0.02ohm.cm, that is, the doping concentration is 6.33e18 / cm 3 -1.22e18 / cm 3 If the substrate is directly in contact with the back metal, a good ohmic contact cannot be formed. The conventional process is to thin the back surface after the front process is completed, then perform back implantation, anneal, and re-grow the back metal to increase the back surface of the substrate. Concentration, reduce the con...
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IPC IPC(8): H01L21/336H01L21/265H01L21/02
CPCH01L21/02164H01L21/0217H01L21/26586H01L29/66712
Inventor 赵秋森陈晓伦许柏松徐永斌
Owner 江苏新顺微电子股份有限公司