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ldpc decoding method suitable for nand flash memory

An LDPC code and decoding technology, applied in the field of LDPC decoding, can solve the problems that NAND flash memory systems cannot be obtained and require short delays, etc.

Active Publication Date: 2021-09-14
SHANDONG SINOCHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the improved algorithm of general bit flipping requires the help of soft information such as the reliability information of the received bits, which cannot be obtained in the NAND flash memory system.
[0008] 4. The delay is required to be short, and the decoding needs to have a parallel structure

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  • ldpc decoding method suitable for nand flash memory
  • ldpc decoding method suitable for nand flash memory
  • ldpc decoding method suitable for nand flash memory

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Embodiment Construction

[0030] The present invention will be further defined below in conjunction with the accompanying drawings and specific embodiments.

[0031] Such as figure 2 As shown, it is a flow chart of the LDPC decoding method suitable for NAND flash memory described in this embodiment, and the method includes the following steps:

[0032] S01), assuming that the code length of the LDPC code is N, the information bit length is K, and its check matrix H mn is an M ×N sparse matrix [h mn ], M, N, K are positive integers greater than 0, 0≤m≤M-1, 0≤n≤N-1, H mn There are γ 1s in each column, ρ 1s in each row, γ and ρ are integers greater than or equal to 0, the size of the check matrix is ​​M*N, and each row uses h 0 , h 1 , ……, h M-1 means that h j = ( h j，0 , h j，1 , ……, h j（N-1）), 0≤j mn The set of columns where the 1 in the mth row is recorded as N(m)={n:h mn = 1}; the set of check equations that the nth bit participates in is the check matrix H mn The set of rows where the 1...

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Abstract

The invention discloses an LDPC decoding method suitable for NAND flash memory, introduces a new judgment variable En, and obtains performance superior to that of a bit flipping algorithm on the basis of not significantly increasing the amount of calculation. For NAND flash memory circuits, the new error correction algorithm has the following advantages: low logic complexity, simple programming circuit; only real number operations are required, no floating-point operations or multiplication and division operations, low power consumption for operations; suitable for parallel structures, low operation delay ; The flipping threshold is adjustable. By adjusting the threshold, a dynamic balance between delay and error correction performance can be achieved.

Description

technical field [0001] The invention relates to an LDPC decoding method, in particular to an LDPC decoding method suitable for NAND flash memory. Background technique [0002] With the continuous development of microelectronics technology, the storage density of NAND flash memory has increased significantly, resulting in a sharp increase in bit error rate. The traditional error correction code architecture can no longer meet the error correction requirements of NAND flash memory. Low-Density-Parity-Check Code (Low-Density-Parity-Check Code, LDPC) has attracted a lot of research in recent years because of its excellent performance close to the Shannon limit and low decoding complexity, and has been adopted by 802.16e, DVBS2, digital broadcasting and other digital communication systems have been adopted one after another. In recent years, LDPC codes have also been discussed by scholars as error-correcting codes on NAND flash memory, hoping to reduce the ever-increasing data b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10H03M13/11
CPCG06F11/1048H03M13/1148
Inventor 裴永航高美洲
Owner SHANDONG SINOCHIP SEMICON