A grid modulation circuit of ldmos solid-state power amplifier
A solid-state power and modulation circuit technology, which is applied in the direction of adjusting electrical variables, instruments, control/regulation systems, etc., can solve the problems of LDMOS device shutdown tailing phenomenon, power amplifier modulation pulse output, etc., and achieve adjustable gate voltage amplitude , high reliability, convenient effect
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Embodiment 1
[0022] Such as figure 1 as shown, figure 1 It is a circuit diagram of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention; the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention includes an adjustable voltage stabilized power supply, a buffer, a turn-on circuit, and a turn-off circuit.
[0023] Specifically, the adjustable regulated power supply includes a first resistor R1, a potentiometer RP1, a first energy storage capacitor C1, a second energy storage capacitor C2, and a voltage regulator U1.
[0024] The voltage regulator U1 includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, and an eighth pin, and the first pin One pin is an en pin, the second pin is a gnd pin, both the third pin and the fourth pin are in pins, and the fifth pin and the sixth pin are both The vout pin, the seventh pin is the sen pin, and the eighth pin is the adj pin.
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Embodiment 2
[0039] Specifically, the specific working principle of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention is that the output voltage of the voltage regulator U1 can be adjusted through the first resistor R1 and the potentiometer RP1, and the appropriate The resistance value of the first resistor R1 and the potentiometer RP1 can control the output voltage range of the voltage regulator U1 between 0.8V-5V.
[0040] When the external TTL modulation signal is at a low level, the first output terminal of the buffer U2 outputs a low level, the second output terminal outputs a high level, the open transistor V1 is cut off, and the off transistor V3 is turned on, the gate voltage of the LDMOS tube is 0V, and the LDMOS tube is cut off, so as to ensure that the LDMOS solid-state power amplifier is in the cut-off state, and there is no signal output, which ensures a reliable cut-off; when the external TTL modulation signal is high level , the fi...
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