A chemical mechanical polishing process modeling method and device for a high-k metal gate

Abstract

The present application discloses a chemical mechanical polishing process modeling method and device for a high-k metal gate. The modeling method and device include: integrating the surface topography of the terminated surface after grinding of the interlayer dielectric layer into the metal grid modeling process, and establishing a chemical mechanical grinding process simulation model of the metal grid. In this way, the modeling method takes into account the influence of the surface topography of the underlying structure (i.e. the interlayer dielectric layer) of the high-k metal gate device on the surface topography of the upper structure (i.e. the metal gate), thereby more accurately and reliably simulating the high-k metal Therefore, this modeling method considers the lamination effect of the surface topography of the high-k metal gate, and the simulation model of the chemical-mechanical polishing process of the high-k metal gate obtained by this modeling method can be It can more accurately reflect the real process of high-k metal gate chemical mechanical polishing, and can more accurately simulate real-time changes in chip surface topography and pattern-dependent surface defects.

Description

Technical field [0001] The present application relates to integrated circuit manufacturing technology, and more particularly relates to a high-k metal gate CMP process modeling method and apparatus. Background technique [0002] Into the 28 nm technology node, high-k metal gate (high-k metal gate, HKMG) as a mainstream technology continue to follow Moore's Law. Although the 14nm node industry-wide three-dimensional structure of the FinFET device to reduce power consumption, area, replacing planar device structure, but still HKMG different nodes, each play different roles at different stages. [0003] Currently, the industry mainly HKMG device structure "gate" process, mainly because "gate" process step need not subjected to high temperatures, and can be arranged more freely formulated work function of the gate electrode material, such that the stability of the chip higher performance and reliability. However, a "gate" process and the difficulties faced by more process design cons...

AI Technical Summary

Problems solved by technology

However, the "gate-last" process faces more process difficulties and design restrictions. The flatness of the metal surface is extremely difficult to meet the standard. Incomplete grinding in the chemical mechanical planarization (CMP) step will result in incomplete removal of the metal. This can cause a short in the circuit; over-polishing can result in a thinner gate electrode, resulting in excessive gate resistance and potential contact over-etch

Additionally, severe overpolishing can expose adjacent source / drain regions to attack during subsequent dummy gate etch removal.

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