Semiconductor structures and methods of forming them

Abstract

A semiconductor structure and a method for forming the same, the method comprising: a substrate having a first gate structure and a second gate structure on the substrate, the substrate between the first gate structure and the second gate structure has a spacer region, and on the substrate, There is a dielectric layer on the sidewall and top of the first gate structure and the sidewall and top of the second gate structure, and a stop layer is provided on the dielectric layer; the stop layer and part of the dielectric layer on the spacer are removed, and the stop layer and the dielectric layer are removed. A first opening is formed in the first opening, and the spacer dielectric layer is exposed at the bottom of the first opening; the stop layer on the second gate structure is removed until the top of the dielectric layer on the second gate structure is exposed, and the top of the second gate structure is exposed. forming a second opening in the stop layer, and the second opening communicates with the first opening; using the stop layer as a mask, etching the dielectric layer at the bottom of the first opening and the second opening until the spacer substrate and the second gate structure are exposed surface, forming a third opening in the dielectric layer. The formed device has better performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of semiconductor process technology, such as the introduction of high-K gate dielectric layer, stress engineering technology, ion implantation in pocket regions, and continuous optimization of materials and device structures, the size of semiconductor devices continues to shrink. However, when the feature size of the device is further reduced, planar transistors face huge challenges due to the more significant short-channel effect, manufacturing variation, and reduced reliability. Compared with planar transistors, fin field effect transistors have fully depleted fins, lower dopant ion concentration fluctuations, higher carrier mobility, lower parasitic capacitance, and higher area utilization efficiency, thus received widespread attention. [0003] In ...

AI Technical Summary

Problems solved by technology

[0004] However, in the process of forming the contact hole connecting the active region, other devices are damaged, and the performance of the formed semiconductor device is poor.

Images