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A circuit for realizing clock synchronization of satellite information receiving single computer in burst mode

A technology of information receiving and burst mode, applied in the aerospace field, can solve the problems of uplink data errors and omissions, difficult uplink signal and local clock synchronization, etc., and achieve the effect of strong fault tolerance, simple structure, and reliable execution

Inactive Publication Date: 2018-12-18
SHANGHAI SATELLITE ENG INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, there are two ways to send ground uplink data to satellites: regular transmission and burst. In comparison, in the burst mode, it is more difficult for a stand-alone satellite information receiver to synchronize the uplink signal with the local clock, so there is a certain probability Leading to errors and omissions of upstream data

Method used

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  • A circuit for realizing clock synchronization of satellite information receiving single computer in burst mode
  • A circuit for realizing clock synchronization of satellite information receiving single computer in burst mode

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Embodiment Construction

[0012] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0013] see figure 1 , a circuit design to realize the clock synchronization of the on-board information receiving stand-alone machine in the burst mode, including: figure 1 In the on-board information receiving stand-alone clock synchronization circuit shown, the feedback circuit part can form an appropriate number of addition and subtraction pulses to complete the synchronization between the local clock and the input data signal.

[0014] Specifically, when the local clock of the on-board information receiving stand-alone machine is faster than the code word of the input remote control information, the subtraction pulse is adopted, which is to shield figure 1 Open the normally open NAND gate to reduce the pulse, and then reduce the pulse in a subsequent cycle until the clock code synchronization is completed; when the local clock of the stand-alone machine is slowe...

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Abstract

The invention discloses a circuit for realizing clock synchronization of satellite information receiving single machine in burst mode. The feedback circuit part of the circuit can form appropriate number of addition and subtraction pulses to complete synchronization of local clock and input data signal. Specifically, when the local clock of the satellite information receiving unit is faster than the input remote control information codeword, the pulse is subtracted by shielding the normally open NAND gate to subtract the pulse, and then the pulse is cycled down until the clock code synchronization is completed. When the local clock of a single computer is slower than the input remote control information codeword, the pulse is added by opening the normally closed NAND gate, and the pulse isadded by subsequent cycles until the synchronization is completed. The invention can complete the synchronization of the local clock of the information receiving unit and the input data signal in thesatellite burst mode, and has the advantages of strong fault tolerance, high reliability, simple structure and simple use.

Description

technical field [0001] The invention relates to the field of aerospace, in particular to a circuit for realizing the clock synchronization of a single machine receiving information on a satellite in a burst mode. Background technique [0002] At present, there are two ways to send ground uplink data to satellites: regular transmission and burst. In comparison, in the burst mode, it is more difficult for a stand-alone satellite information receiver to synchronize the uplink signal with the local clock, so there is a certain probability Leading to errors and omissions of uplink data. [0003] The present invention proposes a circuit design for synchronizing the clock synchronization of the satellite information receiving stand-alone in the burst mode, which can quickly realize the synchronization of the local clock of the satellite information receiving stand-alone and the input data signal in the burst mode, and has strong fault tolerance , which can better guarantee the rel...

Claims

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Application Information

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IPC IPC(8): H04L7/00H04B7/185
CPCH04B7/1851H04L7/0087
Inventor 胡永勤王天亮薛大伟
Owner SHANGHAI SATELLITE ENG INST
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