A vdmos device and its manufacturing method

Abstract

The invention relates to a VDMOS device and a manufacturing method thereof. The method comprises: sequentially growing a gate oxide layer and a polysilicon layer on the surface of the gate oxide layer and having a first opening on the upper surface of the epitaxial layer; A body region of the second conductivity type is formed in the region; a first dielectric layer is formed on the gate oxide layer and the upper surface of the polysilicon layer; a plurality of source region photoresists are formed in the first opening, for the first A dielectric layer is wet-etched to remove the first dielectric layer not covered by the photoresist in the source region and the part of the first dielectric layer covered by the photoresist in the source region, and the remaining first dielectric layer layer is the second dielectric layer; the gate oxide layer is dry-etched to remove the gate oxide layer except under the photoresist in the source region to form a stepped source region implantation window; through implantation and thermal In a driving process, a source region of the first conductivity type is formed in the surface region of the body region.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, and is specifically a VDMOS device and its production method thereof. Background technique [0002] VDMOS (Vertical Double Double Double Double Diffusion Metal Oxide Semiconductor) There is a very important parameter, EAS (Monopulse Avalanchenergy, single-pulse buffer uniform), which is defined as a single avalanche. The maximum energy consumed. In applications where the source and drain generate larger voltage spikes, the avalanche energy of the device must consider the avalanche energy, EAS is a very important parameter for measuring the VDMOS device. [0003] The EAS failure of the general device has two modes, thermal damage and parasitic triode conduction damage. Parasitic triode conduction damage means that the device itself has a parasitic triode (an epitaxial-body area-source region), when the device is turned off, when the reverse current flow of the source leakage, generates a...

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Problems solved by technology

The conduction damage of the parasitic triode means that there is a parasitic triode (epitaxial layer-body region-source region) in the device itself. When the device is turned off, when the reverse current between the source and drain flows through the body region, a voltage drop occurs. If this If the voltage drop is greater than the turn-on voltage of the parasitic transistor, the reverse current will turn on the parasitic transistor due to the amplification effect of the transistor, resulting in loss of control. At this time, the gate voltage can no longer turn off the VDMOS

[0004] In the current manufacturing method, since the source region is located between the polycrystalline gates, the proportion of the source region to the body region is too large, which greatly affects the overall resistance of the body region, and it is difficult to improve the limit EAS of the device, which in turn affects the device performance. promotion

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