A design method of YOLO network forward inference accelerator based on FPGA

Abstract

The invention provides a design method of YOLO network forward inference accelerator based on FPGA. The accelerator comprises an FPGA chip and a DRAM. The memory BRAM in the FPGA chip is used as a data buffer, and the DRAM is used as a main storage device. The accelerator design method comprises the following steps: (1) quantizing the original network data by 8 bits to obtain a decimal point position which has the least influence on the detection accuracy, and forming a quantization scheme, wherein the quantization process is carried out layer by layer; (2) parallel computation of YOLO's nine-layer convolution network with FPGA chip; (3) position mapping. The invention solves the technical problem that the storage resources on the FPGA chip in the prior art do not grow as fast as the neural network scale, and the general target detection network is difficult to be transplanted to the FPGA chip according to the traditional design thinking, so as to achieve the purpose of using fewer resources on the chip to achieve faster speed.

Description

technical field [0001] The invention relates to the technical field of deep learning and hardware structure design, in particular to a design method for forward reasoning acceleration of a target detection network on an FPGA. Background technique [0002] In recent years, machine learning algorithms based on convolutional neural networks (Convolutional Neutral Network) have been widely applied to computer vision tasks. However, for large-scale CNN networks, the characteristics of intensive computation, intensive storage, and large resource consumption have brought great challenges to the above tasks. It is difficult for traditional general-purpose processors to meet the practical requirements in the face of such high computing pressure and large data throughput. Therefore, hardware accelerators based on GPU, FPGA, and ASIC have been proposed and widely used. [0003] FPGA (Field Programmable Gate Array) field programmable gate array is a product of further development on th...

AI Technical Summary

Problems solved by technology

[0005] The existing FPGA-based neural network accelerators often store all the intermediate calculation results of the network layer in the on-chip static memory, and store the weights required by the network in the off-chip dynamic memory. Limits the size of the network that can be accelerated

At this stage, as the requirements for task complexity and precision become hig

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