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A method for manufacturing an isolation structure of an LDMOS

A manufacturing method and isolation structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as concentration, uneven electric field distribution, and lateral voltage breakdown

Active Publication Date: 2019-01-15
CSMC TECH FAB2 CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The two side walls of the general shallow trench isolation structure are parallel and vertically distributed, which will cause the electric field to concentrate at the bottom of the shallow trench isolation structure near the corner of the source region, making the electric field distribution between the source region and the drain region uneven , and will cause a new dense electric field at the middle of the bottom of the shallow trench isolation structure and the corner far away from the source region, and lateral voltage breakdown is prone to occur at the new dense electric field

Method used

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  • A method for manufacturing an isolation structure of an LDMOS
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  • A method for manufacturing an isolation structure of an LDMOS

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Embodiment Construction

[0018] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] The se...

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Abstract

The invention relates to a method for manufacturing an isolation structure of an LDMOS, comprising the steps of: forming a first trench on a wafer surface; Filling the first trench with silicon oxide;Removing a portion of the silicon oxide surface in the first trench by etching; Forming a silicon oxide corner structure at a corner at the top of the first trench by thermal oxidation; Depositing anitrogen-containing compound on the wafer surface to cover the silicon oxide surface and the silicon oxide corner structure surface in the first trench; Dry etching the nitrogen-containing compound toremove the nitrogen-containing compound on the silicon oxide surface in the first trench to form the nitrogen-containing compound sidewall residue; A second trench is formed by further etching downward with the residual nitrogen-containing compound sidewall as a mask. The second trench is formed by etching downward with the nitrogen-containing compound sidewall as a mask. Forming a silicon oxidelayer on the sidewalls and bottom of the second trench; Removing the residue of nitrogenous compound sidewall; The first trench and the second trench are filled with silicon oxide. The invention can improve the breakdown voltage and save the lithographic plate.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing an LDMOS (Lateral Double Diffusion Metal Oxide Semiconductor Field Effect Transistor) isolation structure. Background technique [0002] The Shallow-Trench-Isolation (STI) process is introduced into the drift region of the LDMOS (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor) device, and the length of the drift region can be extended vertically to the substrate while reducing the length of the device. The area is reduced, and at the same time, STI reduces the electric field of the gate / drain of the device, reduces the parasitic capacitance, and significantly improves the optimization window of the device withstand voltage BVdss and on-resistance Ron,sp. [0003] The two side walls of the general shallow trench isolation structure are parallel and vertically distributed, which will cause the electric field to concent...

Claims

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Application Information

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IPC IPC(8): H01L21/762
CPCH01L21/76232H01L21/02164H01L21/02255H01L21/02274H01L21/0337H01L21/76235H01L29/0653H01L21/0217H01L21/31116H01L21/31144H01L29/66704
Inventor 祁树坤孙贵鹏
Owner CSMC TECH FAB2 CO LTD
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