A circuit path delay fluctuation prediction method based on machine learning

Abstract

The invention discloses a circuit path delay fluctuation prediction method based on machine learning, which comprises the following steps: S1, selecting an appropriate sample characteristic quantity by analyzing the relationship between the circuit characteristic and the path delay; S2, generating random paths by enumerating the values of the randomized parameters, obtaining the path maximum delaythrough Monte Carlo simulation of the random paths, selecting the reliable paths through the 3 sigma standard, and taking the sample characteristic quantity and the path delay of the reliable paths as a sample set; 3, establishing a path delay prediction model and adjusting parameter of that model; S4, verifying the accuracy and stability of the path delay prediction model; S5: obtaing the path delay. The invention has the advantages of high precision and low running time, and has obvious advantages in accuracy and efficiency of time series analysis.

Description

technical field The invention relates to the field of integrated circuits, in particular to a method for predicting circuit path delay fluctuations. Background technique With the rise of smart devices such as the Internet of Things and wearables, the key technology of extremely low voltage is an important enabling technology, and its design methodology has become a research hotspot in industry and academia. Compared with conventional voltage and sub-threshold voltage, near-threshold circuits have significant energy-efficiency advantages, which have aroused great interest in industry and academia, but PVT deviations at near-thresholds cause path delay deviations to multiply, making circuit performance critical. The deterioration greatly offsets the energy efficiency bonus brought by the near-threshold circuit. In the traditional path-based static timing analysis method, the path delay is calculated by establishing a feature library for each combinational logic unit in the p...

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Problems solved by technology

Compared with conventional voltage and sub-threshold voltage, near-threshold circuits have significant energy-efficiency advantages, which have aroused great interest in industry and academia, but PVT deviations at near-thresholds cause path delay deviations to multiply, making circuit performance critical. deterioration, which greatly offsets the energy efficiency bonus brought by the near-threshold circuit

In the traditional path-based static timing analysis method, the path delay is calculated by establishing a feature library for each combinational logic unit in the path, but this method has defects. On the one hand, the unit delay deviation is non-Gaussian distribution near the threshold , it is difficult to calculate the path delay by linear accumulation method, on the other hand, the path delay is too pessimistic due to failure to consider the correlation of unit delay time

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