Package structure and manufacturing method thereof

Abstract

The invention discloses an encapsulation structure and a manufacturing method thereof. The encapsulation structure comprises a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a wafer, a circuit layer structure and an insulating protection layer. The composite layer of non-conductive inorganic material and organic material is arranged on the metal layer. The sealant is combined on the composite layer of non-conductive inorganic material and organic material. The chip is embedded in the encapsulant, and the chip has a plurality of electrode pads. The wiring layer structure is formed on the encapsulant and the wafer. The circuit layer structure includes at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer, and the bottommost circuit layer is electrically connected to the electrode pad through the conductive blind holes. The insulation protection layer is formed on the circuit layer structure. The insulating protection layer has a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. The invention can strengthen the overall structural strength to prevent warpage.

Description

technical field [0001] The invention relates to a packaging structure and a manufacturing method thereof. Background technique [0002] With the evolution of semiconductor packaging technology, in addition to the traditional wire bonding (Wire bonding) semiconductor packaging technology, different packaging types have been developed for semiconductor devices, such as directly embedding in the package substrate. And electrically integrate semiconductor chips with integrated circuits to reduce the overall volume and improve electrical functions. [0003] In order to meet the requirements of shortening the length of wires, reducing the thickness of the overall structure, and responding to the trend of high frequency and miniaturization, a method of processing embedded chip substrates based on a coreless carrier board has been developed. However, since the load-bearing board without a core layer lacks a hard core board body for support, the strength is insufficient, and thus th...

AI Technical Summary

Problems solved by technology

However, since the load-bearing plate without core layer lacks a hard core plate for support, resulting in insufficient strength, the overall structure is prone to warpage

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