System and method for detecting good product of integrated circuit

Abstract

The invention belongs to the technical field of chip testing, and specifically provides a system and method for detecting good products of integrated circuits, which are used to realize intelligent testing of multiple chips. The invention includes a control device, a display device, a decoder and several chips to be tested; the display device is connected to control transposition for displaying the detection results; the chip selection signal ports of several chips to be tested are connected to the control device through the decoder, Moreover, the clock interface and the data transmission interface of each chip to be tested are correspondingly connected to the same interface of the control device. The present invention adopts the multiplexing technology of the clock interface and the data transmission interface of the chip to be tested, matches the decoder at the CS side of the chip to be tested, and realizes n io port pairs of the control device. n The control of each chip to be tested effectively overcomes the problem of requiring a large number of IO ports in multi-chip testing; at the same time, the test process is optimized, the test time is greatly shortened, and the test efficiency is effectively improved; that is, high-efficiency, low-cost multi-chip intelligent testing.

Description

technical field [0001] The invention belongs to the technical field of chip testing, and relates to an intelligent, efficient, multi-chip, and less-channel testing system and method, in particular to a system and method for detecting good-quality integrated circuits. [0002] technical background [0003] Flash memory is used in computers and electronic equipment, automobiles, Internet of Things, drones, smart homes and other devices. These applications make flash most demanding higher transmission speed and lower power consumption; flash interface is extended from SPI To OPI (Octal SPI), by increasing the data transmission channel of serial nor flash, and supporting single, dual, quad or octal I / O interface; because Octal SPI is used to transmit data IO increased from 2 SPI to 8 , while the transmission data speed increases, the previous tests also need to occupy a large number of IO ports. [0004] Traditional chip testing requires manual control, especially the testing of...

AI Technical Summary

Problems solved by technology

[0005] DFT technology is to implant some special structures into the circuit during the design stage, so that the test can be performed after the design is completed; by adding testability design structures, such as scan chains, BIST (build-in-self-test), etc., internal signals can be exposed to Outside the circuit; such as: BIST testing technology is widely used in the semiconductor industry. The BIST technology used in the memory includes implanting the test pattern generation circuit, sequential circuit, mode selection circuit and debugging test circuit in the circuit. However, implanting BIST in the chip will cause Occupies additional circuit area, additional pins, increases chip cost, and may have test blind spots

[0006] ATE (Automatic Test Equipment) uses MCU, PLC, PC based on VB, VC development platform, uses Test Stand&LabVIEW and JTAG / Boundary Scan and other technologies to develop and design various types of automated test equipment according to customer's test requirements, drawings and reference schemes; The cost of ATE testing is extremely high, and the test items need to be negotiated with the test factory, so it is extremely inconvenient to increase or decrease the test items

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