A Low Dropout Mirror Current Source Circuit

Abstract

The invention discloses a low-dropout mirror current source circuit. The low-dropout mirror current source circuit comprises a first PMOS (positive channel metal oxide semiconductor) tube P1 and a second PMOS tube P2 in mirror symmetry, and a first reference current source I1, a second reference current source I2, a first NMOS tube N1, and a second NMOS tube N2; one end of the first reference current source I1 is respectively connected with a voltage source VDD, a source of the first PMOS tube P1 and a source of the second PMOS tube P2; an output end of the first reference current source I1 isrespectively connected to a grid of the first PMOS tube P1, a grid of the second PMOS tube P2, and a drain of the second NMOS tube N2; one end of the second reference current source I2 is grounded, and the output end of the second reference current source I2 is respectively connected to the source of the first NMOS tube N1 and the source of the second NMOS tube N2; the drain of the first PMOS tube P1 is connected with the grid of the second NMOS tube N2 and used as a current output end, and the drain of the second PMOS tube P2 is respectively connected to the drain and the grid of the first NMOS tube N1. The required current source dropout can be reduced when more stable output current is realized through the low-dropout mirror current source circuit disclosed by the invention.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a low voltage drop mirror current source circuit. Background technique [0002] In the CMOS process, the traditional mirror current source is composed of two matched MOS transistors, one of which is connected in a diode manner and connected to the reference current source, and the drain of the other MOS transistor is the current output terminal, and its high output resistance is mainly It is guaranteed by the large drain-source voltage of the current output MOS transistor (that is, the voltage drop of the current source) and the long channel length. The power supply voltage of the deep submicron CMOS process has dropped to 1.2V or even lower, and the voltage margin is very tight for analog circuits. For analog circuits that process large signals (input signal amplitude greater than 300mV) such as voltage buffers, the Even more severe, it is becoming more and more difficu...

AI Technical Summary

Problems solved by technology

However, the current source voltage drop required for them to work properly is larger: the minimum voltage drop of the Wilson mirror current source and the cascode mirror current source is equal to the sum of the gate-source voltage and the drain-source saturation voltage (V GS +V DSAT ), the minimum voltage drop of the improved low-voltage cascode mirror current source is also theoretically 2V DSAT So large, that is, these three improved structures improve the traditional mirror current source at the cost of increasing the voltage drop of the current source, which does not meet the requirements of advanced CMOS process development.

In fact, the performance of these mirror current sources when working near the minimum voltage drop is poor, and the traditional mirror current sources that work normally under the deep submicron CMOS process require a voltage drop of at least about 250 mV

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