3D memory device and manufacturing method thereof

Abstract

The invention discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a substrate, a laminated structure located above the substrate and comprising a pluralityof gate conductors and a plurality of interlayer insulating layers, which are stacked alternately, a plurality of channel columns penetrating through the laminated structure, and conductive channels penetrating through the laminated structure; the conductive channels are connected to the bottom ends of the channel columns through the substrate, and are spaced from the gate conductors by adopting oxide layers; the 3D memory device further comprises barrier layers; and the barrier layers are used for spacing the conductive channels from the oxide layers. The barrier layers in the 3D memory device can increase the thicknesses of the equivalent oxide layers between the gate conductors and the conductive channels, and a breakdown voltage is increased, so that the yield and reliability of the 3Dmemory device are improved.

Description

technical field [0001] The present invention relates to memory technology, and more particularly, to 3D memory devices and manufacturing methods thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared w...

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Problems solved by technology

However, silicon oxide is easily oxidized during deposition (eg Figure 1c Middle dotted line), and the density is low, so that the breakdown voltage between the gate conductor and the conductive channel is low, resulting in poor electrical performance of the 3D memory device

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