Semiconductor device
A semiconductor and substrate technology, applied in semiconductor devices, transistors, electrical solid devices, etc., can solve problems such as insufficient suppression of voltage vibration and poor electrical connection reliability.
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no. 1 Embodiment approach
[0030] First, refer to figure 1 A schematic configuration of the semiconductor device 100 of this embodiment will be described.
[0031] The semiconductor device of this embodiment is used, for example, in a switching circuit in which a plurality of reverse conducting insulated gate bipolar transistors (RC-IGBTs) are connected in parallel to obtain an output current.
[0032] figure 1 This is an equivalent circuit of the semiconductor device 100 of this embodiment. Such as figure 1 As shown, the semiconductor device 100 is formed by connecting two sets of switching elements 110 connected in series between a power supply VCC and a ground potential (GND) as a reference potential. That is, the plurality of switching elements 110 are connected in parallel to the power supply VCC. The switching element 110 includes an IGBT element Tr. In the present embodiment, two IGBT elements Tr are connected in parallel between the power supply VCC and the output OUT. The collector ter...
no. 2 Embodiment approach
[0063] In the first embodiment, combining Figure 4 An example in which the active trench gates G1 are formed in the non-cell region 113 at the same interval as the trench gates in the cell region 111 has been described. On the other hand, the semiconductor device 100 of this embodiment is as Figure 8 As shown, compared with the cell region 111, the active trench gate G1 is formed at a narrower interval in the non-cell region 113.
[0064] In other words, the active trench gates G1 in the non-cell region 113 are formed at a higher density than the active trench gates G1 in the cell region 111 in at least a part of the region.
[0065] As a result, the contact area between the active trench gate G1 and the base region 13 via the insulating film can be increased, so that the parasitic capacitance C can be increased.
no. 3 Embodiment approach
[0067] In the first embodiment, combining Figure 4 An example in which the active trench gate G1 is formed in the non-cell region 113 to the same depth as the trench gate in the cell region 111 has been described. On the other hand, the semiconductor device 100 of this embodiment is as Figure 9 As shown, the active trench gate G1 is formed deeper in the non-cell region 113 than in the cell region 111 .
[0068] In other words, the active trench gate G1 in the non-cell region 113 reaches a deeper position in the semiconductor substrate than the active trench gate G1 in the cell region 111 in at least a part of the region.
[0069] As a result, the contact area between the active trench gate G1 and the base region 13 via the insulating film can be increased, so that the parasitic capacitance C can be increased.
[0070] The parasitic capacitance C can be increased more effectively by increasing the formation density of the active trench gate G1 and making the formation depth...
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