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On-chip network optimization method based on approximate calculation

An on-chip network and optimization method technology, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve the problem of not using the tolerance of application programs, so as to improve the congestion situation, optimize the overall performance and energy consumption, and reduce the network The effect of delay

Active Publication Date: 2019-03-29
SOUTH CHINA UNIV OF TECH +1
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The above patent application only optimizes the network by adjusting the positional relationship of the IP core in the on-chip network, and does not take advantage of the tolerance of the application program for errors in the output

Method used

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  • On-chip network optimization method based on approximate calculation
  • On-chip network optimization method based on approximate calculation
  • On-chip network optimization method based on approximate calculation

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Embodiment Construction

[0041] The present invention will be further described in detail below in conjunction with the embodiments and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

[0042] see Figure 4 , C represents the processor core in the network on chip node, M represents the processor Cache (cache memory), R represents the router, and NI represents the network interface. The on-chip network optimization method based on approximate calculation of the present invention includes several parts: a flow predictor, a data clipper, a data restorer, a global controller and a local controller. in:

[0043] Such as figure 1 As shown, the traffic predictor runs on each node L, and at the beginning of each regulation interval, according to the past operating conditions of the node, predicts the communication situation of the data flow sent by the node in the interval, and sends it to the master Control node G.

[0044] Each node of the network on chip i...

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Abstract

The invention discloses an on-chip network optimization method based on approximate calculation. The on-chip network optimization method based on the approximate calculation comprises a data clipper,a data restorer, a flow predictor, a global controller, and a local controller; the data clipper clips the data before a data packet is injected into a network port to shorten the data packet length;the data restorer recovers the lost data after receiving a clipped data packet; the flow predictor predicts data flow in a next regulation interval based on past node communication conditions; the global controller is used for calculating an approximately calculated optimal configuration of each node based on global information and user quality requirements under a global viewing angle, and sending control information to each node; and the local controller performs data loss rate configuration on each data packet waiting to be injected into the network according to the received control information. The on-chip network optimization method based on the approximate calculation can optimize the performance and power consumption of the on-chip network at a low cost without violating the requirements for output quality of the user.

Description

technical field [0001] The invention relates to the technical field of network optimization, in particular to an on-chip network optimization method based on approximate calculation. Background technique [0002] In the context of the flattening of semiconductor process upgrades, many-core chips are an effective design to improve system performance-power consumption ratio. Facing the requirements of many-core chips in communication bandwidth, low power consumption, and scalability, etc., network-on-chip is considered to be a promising technology. Many popular applications in fields such as image processing and machine learning have the characteristics of large data communication volume and tolerance of certain output error. Therefore, approximate computing is a new computer design idea, by relaxing the requirements for accuracy of results , to improve system performance or save system energy consumption. However, the error tolerance of the application is not or seldom util...

Claims

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Application Information

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IPC IPC(8): H04L12/24H04L12/26H04L12/823H04L12/933H04L47/32
CPCH04L41/0823H04L41/145H04L41/147H04L43/0882H04L47/32H04L49/109H04L41/142
Inventor 肖思源王小航潘文明
Owner SOUTH CHINA UNIV OF TECH
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