Semiconductor chip

Abstract

Provided is a semiconductor chip, using a nano wire FET, that has a layout configuration effective in facilitating easy manufacturing. A semiconductor chip (1) is provided with: a first block (100) that includes a standard cell (110) having a nano wire FET; and a second block (400) that includes a nano wire FET. On the first and second blocks (100, 400), the arrangement pitch, in the Y direction,of nano wires (111, 411) extending in the X direction is an integral multiple of a pitch P1, and the arrangement pitch, in the X direction, of pads (112, 412) is an integral multiple of a pitch P2.

Description

technical field [0001] The present disclosure relates to a semiconductor chip including a standard cell using a nanowire FET (Field Effect Transistor, Field Effect Transistor). Background technique [0002] It is known that there is a standard cell method as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell method refers to the following method, that is, the basic cells with specific logic functions (such as inverters, latches, flip-flops, full adders, etc.) are prepared as standard cells in advance, and then multiple standard cells are arranged On the semiconductor substrate, these standard cells are connected by wiring, which is a way to design an LSI chip. [0003] Transistors, which are the basic components of LSI, have achieved increased integration, reduced operating voltage, and increased operating speed by reducing gate length (scaling, proportional reduction). However, in recent years, there has been a problem t...

AI Technical Summary

Problems solved by technology

However, in recent years, there has been a problem that excessive scaling down causes significant increases in off-current and power consumption

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