A convolutional neural network accelerator based on calculation optimization of an FPGA
A convolutional neural network and accelerator technology, applied in the field of convolutional neural network accelerator hardware structure, can solve the problem of large amount of redundant calculation, achieve high computing performance, reduce reading, and improve real-time performance.
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[0029] The technical solutions and beneficial effects of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0030] Such as figure 1 As shown, the hardware structure of the convolutional neural network accelerator designed for the present invention, taking the PE array size 16*16, the convolution kernel size 3*3, and the convolution kernel step size 1 as an example, its working mode is as follows:
[0031] The PC caches the data partitions in the external memory DDR through the PCI-E interface, and the data cache area reads the feature map data through the AXI4 bus interface and caches it in three feature map sub-buffer areas in rows, and the input index value is cached in the feature in the same way Picture buffer area. The weight data read through the AXI4 bus interface is sequentially buffered in 16 convolution kernel buffer areas, and the weight index value is buffered in the convolution kernel buffer area in the same way. T...
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