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High-efficiency heterojunction battery intrinsic amorphous silicon passivation layer structure and preparation method thereof

A technology of intrinsic amorphous silicon and heterojunction cells, applied in circuits, photovoltaic power generation, electrical components, etc., can solve problems such as microvoid defects, solar cell performance deterioration, etc., to avoid epitaxial growth, enhance interface passivation, The effect of increasing the hydrogen content of the film

Inactive Publication Date: 2019-04-16
SUZHOU AIKANG LOW CARBON TECH INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such a high H dilution ratio will not only lead to the bombardment of H ions on the surface of crystalline silicon during the deposition process, forming defects, but also produce epitaxial growth during the deposition of amorphous silicon, forming micro-void defects, which will eventually lead to the deterioration of solar cell performance.

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  • High-efficiency heterojunction battery intrinsic amorphous silicon passivation layer structure and preparation method thereof
  • High-efficiency heterojunction battery intrinsic amorphous silicon passivation layer structure and preparation method thereof

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Embodiment 1

[0031] see figure 1 , the present invention relates to an intrinsic amorphous silicon passivation layer structure for a high-efficiency heterojunction battery, which includes an N-type crystalline silicon wafer 1, and the front and back sides of the N-type crystalline silicon wafer 1 are provided with two layers of amorphous Silicon intrinsic layer 2, that is, the first amorphous silicon intrinsic layer 2 and the second amorphous silicon intrinsic layer 3;

[0032] The thickness of the first intrinsic layer 2 of amorphous silicon is 4nm, and the intrinsic layer 2 of the first amorphous silicon adopts the PECVD method. 2 Depositing, that is, using pure silane to deposit; the thickness of the second amorphous silicon intrinsic layer 3 is 4nm, and the second amorphous silicon intrinsic layer 3 is made of H 2 Diluted S i h 4 are deposited, the H 2 :S i h 4 1:1;

[0033] The first layer of amorphous silicon intrinsic layer 2 uses pure silane to prevent epitaxial growth and H...

Embodiment 2

[0047] see figure 1 , the present invention relates to an intrinsic amorphous silicon passivation layer structure for a high-efficiency heterojunction battery, which includes an N-type crystalline silicon wafer 1, and the front and back sides of the N-type crystalline silicon wafer 1 are provided with two layers of amorphous Silicon intrinsic layer 2, that is, the first amorphous silicon intrinsic layer 2 and the second amorphous silicon intrinsic layer 3;

[0048] The thickness of the first intrinsic layer 2 of amorphous silicon is 3 nm, and the intrinsic layer 2 of the first amorphous silicon cannot pass H through PECVD. 2 Deposition, that is, using pure silane for deposition; the thickness of the second amorphous silicon intrinsic layer 3 is 5nm, and the second amorphous silicon intrinsic layer 3 is made of H 2 Diluted S i h 4 are deposited, the H 2 :S i h 4 2:1;

[0049] The first layer of amorphous silicon intrinsic layer 2 uses pure silane to prevent epitaxial gro...

Embodiment 3

[0063] see figure 1 , an intrinsic amorphous silicon passivation layer structure for a high-efficiency heterojunction battery that the present invention involves, it includes an N-type crystalline silicon wafer 1, and the front and back sides of the N-type crystalline silicon wafer 1 are provided with three layers of amorphous silicon Intrinsic layer 2, that is, the first intrinsic layer of amorphous silicon 2, the second intrinsic layer of amorphous silicon 3 and the third intrinsic layer of amorphous silicon;

[0064] The thickness of the first intrinsic layer 2 of amorphous silicon is 3 nm, and the intrinsic layer 2 of the first amorphous silicon cannot pass H through PECVD. 2 Deposition, that is, depositing by pure silane; the thickness of the second amorphous silicon intrinsic layer 3 is 3nm, and the second amorphous silicon intrinsic layer 3 is made of H 2 Diluted S i h 4 For deposition, the H of the second amorphous silicon intrinsic layer 3 2 :S i h 4 1:1; the th...

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Abstract

The invention relates to a high-efficiency heterojunction battery intrinsic amorphous silicon passivation layer structure and a preparation method thereof, the high-efficiency heterojunction battery intrinsic amorphous silicon passivation layer structure comprises an N-type crystal silicon wafer (1), and the front surface and the back surface of the N-type crystal silicon wafer (1) are respectively provided with a plurality of amorphous silicon intrinsic layers. An amorphous silicon doping layer (4) is arranged on the outer side of a second amorphous silicon intrinsic layer (3), a TCO conductive film (5) is arranged on the outer side of the amorphous silicon doping layer (4), and a plurality of Ag electrodes (6) are arranged on the outer side of the TCO conductive film (5). The amorphous silicon intrinsic layer adopts lamination, the first layer adopts pure silane deposition, epitaxial growth caused by initial deposition of a crystalline silicon / amorphous silicon interface is effectively avoided, and the second layer adopts high-hydrogen diluted silane deposition, so that the hydrogen content of a thin film of the first layer of amorphous silicon is increased, and interface passivation is enhanced at the same time.

Description

technical field [0001] The invention relates to the technical field of high-efficiency photovoltaic cells, in particular to an intrinsic amorphous silicon passivation layer structure of a high-efficiency heterojunction cell and a preparation method thereof. Background technique [0002] With the rapid development of photovoltaic technology, the conversion efficiency of crystalline silicon solar cells is increasing year by year. In the current photovoltaic industry, the conversion efficiency of monocrystalline silicon solar cells has reached more than 21%, and the conversion efficiency of polycrystalline silicon solar cells has reached more than 19%. However, the silicon-based solar cells produced on a large scale and with a conversion efficiency of more than 22.5% are only the Interdigitated Back Contact (IBC) solar cells of SunPower of the United States and the amorphous silicon / crystalline silicon with intrinsic thin layers of Panasonic of Japan. Heterojunction with Intri...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/0352H01L31/0376H01L31/076H01L31/077H01L31/20
CPCH01L31/03529H01L31/03762H01L31/076H01L31/077H01L31/202Y02E10/547Y02E10/548Y02P70/50
Inventor 郭小勇易治凯汪涛王永谦
Owner SUZHOU AIKANG LOW CARBON TECH INST
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