A 6T & 6TPPNN unit layout method based on minimum width constraint

Abstract

The invention discloses a 6T & 6TPPNN unit layout method based on minimum width constraint. The 6T & 6TPPNN unit layout method comprises the following steps: considering unit alignment of Vdd / Vss track alignment constraint; Performing unit clustering based on minimum width constraint; Performing 6TPPNN unit conversion; performing cell movement based on the fragment effect; According to the methodprovided by the invention, on the premise of not increasing any chip design area, the line length increase caused on the basis of reducing all minimum width constraints can be reduced, meanwhile, thefragment effect is reduced, and the circuit performance is improved.

Description

technical field [0001] The invention relates to the technical field of VLSI physical design automation, in particular to a cell layout method. Background technique [0002] In traditional circuit design, standard cells with the same height are easier to design and optimize. Then, as the design complexity increases, the general 6T&6TPPNN unit structure with mixed height can achieve a better balance between area and winding linearity than single-height standard units. Specifically, smaller cell heights result in smaller area and lower power consumption, but at the expense of lower power drive. Conversely, a higher cell height can achieve greater power drive and better windability, but it also requires a larger area and higher power consumption. The circuit design of such mixed-height cells is more challenging due to the heterogeneity of the cell structure. Also, in this layout design, additional consideration needs to be given to aligning multiple row height cells to the co...

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Problems solved by technology

In addition, since 6TPPNN cells are double-height, and they can only be placed on half-rows, each 6TPPNN cell will have half-row fragmentation on the top and bottom sides, which has a significant impact on circuit layout performance

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