Three dimensional semiconductor memory device

Abstract

Provided is a three-dimensional semiconductor memory device. The device may include a substrate that includes a cell array region and a connection region; an electrode structure provided on the substrate to extend in a first direction and include electrodes that are vertically stacked on the substrate and include pad portions which are stacked on the connection region to have a staircase structure; cell vertical structures provided on the cell array region to penetrate the electrode structure; dummy vertical structures provided on the connection region to penetrate the pad portion of each electrode; and cell contact plugs coupled to the pad portions of the electrodes. Each cell contact plug may have a non-circular top surface, and the dummy vertical structures may be arranged to surround each cell contact plug, in a plan view.

Description

technical field [0001] Exemplary embodiments relate to three-dimensional semiconductor memory devices, and in particular, to highly reliable and highly integrated three-dimensional semiconductor memory devices. Background technique [0002] Higher-integration semiconductor devices are required to meet consumer demand for superior performance and low price. In the case of a semiconductor device, increased integration is particularly important because its integration is an important factor in determining product prices. In the case of a conventional two-dimensional or planar semiconductor device, since its integration is mainly determined by the area occupied by a unit memory cell, the integration is greatly affected by the level of fine pattern formation technology. However, the extremely expensive process equipment required to increase pattern fineness sets practical limits to increasing the integration of two-dimensional or planar semiconductor devices. In order to overco...

AI Technical Summary

Problems solved by technology

As far as traditional two-dimensional or planar semiconductor devices are concerned, because their integration is mainly determined by the area occupied by a unit memory cell, integration is greatly affected by the level of fine pattern formation technology

However, the extremely expensive process equipment required to increase pattern fineness sets practical limits on increasing the integration of two-dimensional or planar semiconductor devices

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