Small-area low-power-consumption clock data recovery circuit

Abstract

The invention discloses a small-area low-power-consumption clock data recovery circuit. The clock data recovery circuit comprises a phase frequency detector, a frequency divider, a first charge pump,a second charge pump and a Bang-bang Phase discriminator, a loop filter, a voltage-controlled oscillator and a seventh switch. The input end of a phase frequency detector is connected with input signals and connected with the first output end of the voltage-controlled oscillator through the frequency divider. The input end of the voltage-controlled oscillator is connected with the loop filter, andthe second output end, the third output end, the fourth output end and the fifth output end are connected with the Bang-bang phase discriminator. First to fourth input ends of the bank phase discriminator are connected; A fifth six input end of the bang phase discriminator is connected with positive and negative differential input signals, first to fourth output ends of the bang phase discriminator serve as output ends of the whole circuit, and a fifth output end of the bang phase discriminator is connected with a second charge pump; The second charge pump is connected with a power supply through a seventh switch, and the output end is connected with the second input end of the loop filter. The first charge pump is connected with the phase frequency detector, and the output end of the first charge pump is connected to the first input end of the loop filter. The double-ring alternating working power consumption is low, the area is reduced, and the establishing speed and the noise performance are both considered.

Description

technical field [0001] The invention relates to a clock data recovery circuit with small area and low power consumption, belonging to the technical field of clock data recovery circuits. Background technique [0002] Clock Data Recovery (CDR) is the core module of the high-speed communication interface. Its function is to recover high-quality clock information, and use the recovered clock signal to distort and superimpose the data signal in the transmission process. Perform resampling to recover high-quality data. [0003] The existing CDR design technology usually adopts a double-loop structure: using a Frequency-Locked Loop (FLL for short) to recover the clock frequency, and using a Phase-Locked Loop (PLL for short) to align the clock edge to the data The center, that is, the best sampling point, completes the resampling of the data. In order to keep the result of FLL and apply it to PLL, both loops need to be turned on at the same time. In order to reduce power consump...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to overcome the loss of flexibility caused by the use of double loops in the existing data recovery circuit, the inability to set loop parameters reasonably, and the optimization of CDR performance Restricted by the shortcomings, a small area and low power consumption clock data recovery circuit is provided

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