A Hybrid Analog-to-Digital Converter

Abstract

The present invention provides a hybrid analog-to-digital converter, the hybrid analog-to-digital converter is applied in a first readout circuit, and the first readout circuit has an M×N pixel array structure; the hybrid analog-to-digital converter The device includes M×N first-level ADCs and N second-level ADCs; each pixel of the pixel array structure is arranged with a first-level ADC; each column of the pixel array structure is arranged with a second-level ADC Each of the first-level ADCs is connected to the second-level ADC of the column; the first-level ADC is used to transmit the generated high-bit signal to the second-level ADC; the second-level ADC is used After generating the low-order signal, splicing the high-order signal and the low-order signal and reading it out. The embodiment of the present invention uses a two-stage quantization structure, so that the hybrid analog-to-digital converter obtains better charge handling capability and higher linearity compared with the traditional design.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a hybrid analog-to-digital converter. Background technique [0002] Cooled infrared focal plane arrays (IRFPAs) for optical imaging are used in a wide variety of different fields. Integrating an analog-to-digital converter (ADC) on an IRFPA has become a growing concern because of its high noise performance, short analog lines, and low system-level hardware cost. Therefore, the demand for high-performance digital readout integrated circuits (DROICs) is increasing today for the small pixel pitches required for the long-wave infrared (LWIR) focal plane. [0003] For IRFPA, three ADC configurations have been developed: monolithic, column-level, and pixel-level. Today, the monolithic ADC structure is a mature technology, but its high sampling rate leads to high power consumption and severe noise disturbance, especially when the array size is large. Second, column-level ADCs...

AI Technical Summary

Problems solved by technology

Nowadays, monolithic ADC structure is a mature technology, but its high sampling rate leads to high power consumption and severe noise disturbance, especially when the array size is large

Second, column-level ADCs can provide lower sampling rates, but still have complex parasitic effects

However, conventional folding-integration schemes are often accompanied by the loss of charge

In addition, the counter of the high-resolution ADC will take up huge hardware resources, which means that the pixel pitch has to be increased to accommodate

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