Segmented parallel comparison type ADC

Abstract

The invention discloses a segmented parallel comparison type ADC (Analog to Digital Converter), which belongs to the technical field of electronics and communication and is used for converting an analog signal into a digital signal and comprises the following steps of: firstly, dividing the output of the ADC into a plurality of segments according to bit weights to form output segments with different weight levels; dividing different reference voltages quantized by the reference voltage into a plurality of subsections according to the highest weight level output subsection, and defining the subsections as reference voltage subsections; then, enabling the segment head comparator to generate a comparison value which can be defined as a segment head pointer; On one hand, sending the comparisonvalue to a corresponding trigger and a priority encoder to form a numerical value of a highest weight level output segment, and on the other hand, sending the comparison value to a controllable switch group to control selection of a reference voltage segment from all segments for the first time as a current segment; finally, continuously re-segmenting and re-processing the current segment, or usihng the current segment to form a segment value of the lowest weight level output segment. The conversion speed and the number of bits are increased, and the manufacturing cost is reduced.

Description

technical field [0001] The invention relates to an analog-to-digital converter, which can realize rapid conversion of analog signals to binary numbers, belongs to the field of electronic technology and communication technology, and can be widely used in digital circuit systems such as digital signal processors and single-chip microcomputers. Background technique [0002] Compared with other types of analog-to-digital signal converters (ADC), the parallel comparison A / D converter (also known as Flash ADC) has the advantages of short conversion time and fast conversion speed. However, when the number of conversion bits is large, its hardware The overhead will increase rapidly, and the circuit becomes very complex, so that the manufacture and application of high-bit Flash ADCs are seriously hindered. If the number of binary digits of the conversion output is n, the quantization level of the Flash ADC will be 2 n -1, the required comparators and flip-flops will both be 2 n -1,...

AI Technical Summary

Problems solved by technology

[0003] In order to reduce the cost and improve the application of Flash ADC, a multi-step ADC with sub-ADC calibration is disclosed in Chinese patent 201310596301.0, a 9-stage ten-bit pipeline ADC is disclosed in Chinese patent 201310501026.X, and in China Patent 201710070081.6 discloses an ADC background calibration with double conversion. They all use multi-level ADC conversion, using Flash ADC and / or SAR ADC (successive approximation ADC), but these solutions have no effect on the original Flash ADC structure. No significant innovation

As for other literature, whether it is specifically discussing Flash ADC or discussing multi-level or hybrid ADCs involving Flash ADC, they have not been able to solve the contradiction between hardware cost and conversion speed.

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