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Hash join acceleration method and system based on BRAM in FPGA chip

A technology for accelerating the system and hash table, which is applied in the field of hash connection acceleration method and system, can solve the problem of large occupation and achieve the effect of overcoming the memory bottleneck

Active Publication Date: 2019-08-09
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical task of the present invention is to provide a kind of hash connection acceleration method and system based on the BRAM in the FPGA chip to solve the problem of how to overcome the more CPU calculation and I / O resources occupied in the hash connection software solution.

Method used

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  • Hash join acceleration method and system based on BRAM in FPGA chip
  • Hash join acceleration method and system based on BRAM in FPGA chip
  • Hash join acceleration method and system based on BRAM in FPGA chip

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Embodiment 1

[0049] as attached Figure 1-4 As shown, the hash connection acceleration method based on FPGA on-chip BRAM of the present invention connects multiple dimension tables or multiple columns of the same dimension table to the fact table through multiple channels in parallel, including:

[0050]S100. In the hash connection construction phase, configure a corresponding channel for each dimension table in the FPGA, calculate the hash value of the column data of each dimension table to generate a hash table, and store the column data of the dimension tables with the same hash value Link to the same linked list to generate an address table, and store the above hash table and address table through the FPGA on-chip BRAM;

[0051] S200. In the hash join detection phase, route the fact table to the corresponding channel, calculate the hash value of the column data of the fact table, and connect the row data of the matched fact table and the row data of the dimension table.

[0052] Among...

Embodiment 2

[0066] The present invention provides a hash connection acceleration subsystem based on the BRAM in the FPGA chip, including the BRAM in the FGPA chip configured on the PFGA, a plurality of channels, a hash calculation module, an extraction module, an extraction / hashing module, a verification module and control module.

[0067] Among them, FPGA on-chip BRAM is used to store hash table, address table and database element unit.

[0068] Each channel is assigned a dedicated resource that allows multiple channels of all the above configurations to be processed in parallel during the probing phase of the hash table.

[0069] The hash calculation module is used to calculate the hash value of the column data of the dimension table.

[0070] The extraction module is used to extract database page units for each dimension table.

[0071] The extraction / hash module is used to match the fact table into the corresponding channel, and is used to calculate the column data hash value of eac...

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Abstract

The invention discloses a Hash join acceleration method and system based on a BRAM in an FPGA chip, belongs to the field of database acceleration, and aims to solve the technical problem of how to overcome the defect of large occupancy of CPU calculation and I / O resources in a Hash join software scheme. According to the method, a plurality of dimension tables or a plurality of columns of the samedimension table are connected to a fact table in parallel through a plurality of channels, and the method comprises the steps that in the Hash join construction stage, a corresponding channel is configured for each dimension table in an FPGA, and the Hash tables and address tables are stored through BRAMs in an FPGA chip; and in the Hash join detection stage, the fact table is routed to a corresponding channel, and the line data of the matched fact table is connected with the line data of the dimension table. The structure comprises an FGPA on-chip BRAM configured on a PFGA, a plurality of channels, a Hash calculation module, an extraction module, an extraction / Hash module, a verification module, a connection module and a control module.

Description

technical field [0001] The invention relates to the field of database acceleration, in particular to a hash connection acceleration method and system based on a BRAM in an FPGA chip. Background technique [0002] In modern society, the business decisions of enterprises and the securities transactions of the financial system rely more and more on high-efficiency and low-latency database systems, especially in data query and data analysis, which require high real-time performance. In a relational database, the Join operator, as a frequently executed operation, takes up quite a lot of CPU computing resources. Common Join operators include Sort Merge-Join, Nested Loop-Join, and so on. However, as the size of the database continues to grow, for the sort-merge join, if the result set obtained after applying the predicate conditions specified in the target SQL is large and needs to be sorted, the execution efficiency of the sort-merge join is not high; and For nested loop joins, ...

Claims

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Application Information

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IPC IPC(8): G06F16/21G06F16/22G06F15/78
CPCG06F16/217G06F16/2255G06F16/2282G06F15/7867Y02D10/00
Inventor 齐乐彭福来李凯一吴登勇
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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