High-speed adaptive decision feedback equalizer

Abstract

The invention discloses a high-speed self-adaptive decision feedback equalizer. The high-speed adaptive decision feedback equalizer comprises the following block diagram structures: an even channel Out-even, an odd channel Out-odd, a trigger DFF1, a trigger DFF2, a data selector MUX1, a data selector MUX2, a sampler Dp-0, a sampler Dp-1, a sampler Dn-0 and a sampler Dn-1. Beneficial effects are asfollows: on the premise that the signal and the noise can be effectively separated, the decision feedback device greatly improves the data transmission efficiency by using an ultrahigh-speed linear adder, the chip design area is reduced, the influence of intersymbol interference is reduced, the accuracy in the data transmission process is ensured, and the performance of the equalizer is greatly improved, and the high-speed self-adaptive decision feedback equalizer meets the high-speed requirement of a communication circuit on signal transmission.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a high-speed adaptive decision feedback equalizer. Background technique [0002] With the development of the times and the rise and development of technologies such as the Internet of Things, 5G systems and cloud computing, people have put forward more and more stringent requirements on the power consumption and area of ​​the circuit system, especially for the data transmission rate in the communication system. expectations are growing. The adaptive decision feedback equalizer can deal with the intersymbol interference caused by the channel's limited bandwidth, crosstalk and other non-ideal characteristics. The serial link has gradually become the main link method for communication between chips due to its low price, small footprint, small crosstalk, and the clock signal is embedded in the data information to reduce or eliminate the asynchrony between the clock and data....

AI Technical Summary

Problems solved by technology

[0003] Due to the non-ideality of the circuit PCB board connection, once the transmission data rate is greatly increased, the signal reflection caused by the discontinuity of the transmission line impedance, skin effect, dielectric loss and other factors will cause serious distortion of the transmitted data, that is, We often say inter-symbol interference (ISI), if the data is not processed effectively during line transmission, serious data errors will occur at the receiving end

[0004] The traditional solution is usually to introduce a pre-emphasis circuit in the transmitter chip to correct and eliminate bit errors, but there are two disadvantages in the pre-emphasis circuit: one is that the pre-emphasis circuit needs to introduce a low-loss line between the transmitter and the receiver. The feedback path is used to ensure the normal operation of the adaptive function. However, the introduction of this method not only increases the consumption of hardware, but also makes the circuit more complicated, which is not desirable; the second is that the pre-emphasis circuit reduces the low-frequency signal The amplitude of the high-frequency component is increased to increase the relative amplitude of the high-frequency component, but due to the limitation of the swing of the transmitter drive circuit, this leads to a decrease in the amplitude of the signal received at the receiving end, and at the same time, the noise power is not reduced, thereby reducing the reception signal-to-noise ratio

Both CTLE and FFE belong to linear equalizers. The disadvantage is that they cannot effectively distinguish noise and data to a certain extent, and they will amplify and attenuate the signal and noise in equal amounts (that is, including the influence of crosstalk). As a nonlinear decision feedback equalizer (DFE), it is widely used because it does not amplify noisy signals

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