Cache program operation of three-dimensional storage device with static random access memory

Abstract

An embodiment of a three-dimensional (3D) memory device includes: a 3D NAND memory array having a plurality of pages; an on-die cache coupled to the same chip on which the memory array is located on and configured to cache batches of program data between a host and the memory array, the on-die cache having SRAM cells; and a controller coupled to the on-die cache on the same chip. The controller is configured to: check a state of the (N-2) th batch of program data, N being an integer equal to or greater than 2; program the (N-1) th batch of program data into a corresponding page in the 3D NAND memory array; and cache the Nth batch of program data in the corresponding space in the on-die cache as a backup copy of the Nth batch of program data.

Description

Background technique [0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of manufacturing the same. [0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of planar memory cells approaches the upper limit. [0003] 3D memory architectures can address density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Contents of the invention [0004] Embodiments of 3D memory devices with static random access memory (SRAM) and methods of operating the same are disclosed herein. [0005] In one example, a 3D memory device includes: a 3D NAN...

AI Technical Summary

Problems solved by technology

However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become challenging and costly

As a result, the storage density of planar memory cells approaches the upper limit

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