Multiphase clock generation circuit

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a multi-phase clock generation circuit, which comprises a clock signal output end for generating a high-frequency clock signal; a control signal output end used for generating a control signal; a clock recovery module used for receiving the amplitude of the high-frequency clock signal and generating arecovery high-frequency clock signal; a clock frequency division module used for converting the recovered high-frequency clock signal into a frequency division clock signal; a phase shift module usedfor performing phase shift on the phase of the frequency division clock signal according to the recovered clock signal to generate a clock phase signal; and a phase selection interpolation module usedfor selecting the clock phase signal according to the control signal and performing interpolation operation to obtain a target clock signal. The multi-phase clock is generated by performing phase interpolation on the external input clock, and the clock frequency division module and the phase selection interpolation module are realized by digital logic, so that the multi-phase clock has the beneficial effects of low power consumption and invariable duty ratio.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a multi-phase clock generation circuit. Background technique [0002] At present, in the single-chip ultra-wideband pulse radar system based on the carrier ultra-wideband pulse signal, the main method of receiving the echo pulse is the quantization of equivalent time sampling. The quantization method of equivalent time sampling uses the working principle of ultra-wideband pulse radar to quantify the echo signal in multiple clock cycles, which can reduce the requirements for the analog-to-digital converter while ensuring the sampling rate. Effective time sampling requires a polyphase clock for the ADC. By selecting corresponding sampling clocks in different repetition frequency periods, and then processing the final quantized data, a very high sampling rate can be equivalently obtained, wherein the equivalent sampling rate depends on the time interval betw...

AI Technical Summary

Problems solved by technology

However, the oscillation frequency of the ring oscillator is limited by the process, which will limit the highest equivalent sampling rate it can provide

At the same time, the use of phase-locked loop will also increase the circuit power consumption and area

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