A fault-tolerant architecture for tsv in 3D integrated circuits

Abstract

The present invention is applicable to the field of semiconductor technology, and provides a fault-tolerant architecture for TSVs in three-dimensional integrated circuits. The redundant structure is composed of an N-layer ring structure, and the N-layer ring structure is divided into six regions by six rays, and each ring layer There are three RTSVs in the structure, and the three RTSVs are evenly distributed on the six rays. The RTSVs between adjacent layers are misplaced. The center of the innermost hexagon is equipped with an RTSV, which utilizes the unique symmetry and flexibility of the hexagon. Arrange TSVs in a consistent manner, and select and place RTSVs reasonably, divide the redundant structure into several uniform areas, improve the redundancy rate of each area, and ensure a high repair rate of the entire structure; the uniform distribution of RTSVs in the TSV array, combined with The symmetry of the routing direction can avoid the situation that the repair path length of the faulty TSV is too different or the timing overhead is large, and the overhead can be reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductors and provides a fault-tolerant architecture for TSVs in three-dimensional integrated circuits. Background technique [0002] As the semiconductor process continues to approach the scale of 5nm, 3nm, and 1nm, Moore's Law is also approaching the physical limit. Rico Wiedenbruch, senior vice president of Merck's Global Integrated Circuit Materials Division, said that changing the structure of semiconductor chips through 3D chip structures is the best way to solve the increasingly difficult problem of process size reduction when Moore's Law approaches the physical limit. answer. Three-dimensional integrated circuits (3D IC) use through-silicon vias (Though Silicon Via, TSV) to connect different layers of devices such as different chips or circuit modules in the vertical direction. Compared with two-dimensional integrated circuits, 3D ICs can effectively reduce the length of interconnection lin...

AI Technical Summary

Problems solved by technology

3D chips are prone to faults during the manufacturing process, resulting in the failure to transmit signals normally

In response to this problem, Tingting Hwang et al. proposed a ring redundancy architecture, such as figure 1 As shown, although the area overhead is small, the tolerance to cluster faults is relatively poor, and the fault tolerance rate to 2*2 four faults is only about 50%.

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