A kind of NOR flash memory device and preparation method thereof

Abstract

The invention discloses a NOR flash memory device and a preparation method thereof, wherein the NOR flash memory device comprises a sequentially stacked substrate, a tunnel oxide layer, a floating gate layer, a dielectric layer and a control gate layer; at least one through the control gate layer and the floating gate via hole of the dielectric layer, the floating gate via hole is located in the active area, and is used to expose the floating gate layer to lead out the floating gate electrode; at least one active area blocking structure, the active area blocking structure is arranged on the substrate Between the dielectric layer and the chemical mechanical polishing process on the floating gate layer, it is used to reduce the wear of the floating gate layer exposed by the floating gate via hole. The technical scheme of the present invention can effectively reduce the polishing rate of the floating gate layer around it by the chemical mechanical polishing process by adding a barrier structure in the active region, increase the thickness of the floating gate layer around it, and avoid damage caused by the floating gate layer being too thin. This leads to leakage or breakdown of the NOR flash memory device, which improves the reliability of the NOR flash memory device.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor device technology, and in particular to a NOR flash memory device and a manufacturing method thereof. Background technique [0002] For the floating gate (Floating Gate, FG) NOR flash memory device manufactured by the traditional process of 90 / 65nm node and below, in order to increase the capacitance per unit area of ​​the high withstand voltage capacitor, improve the utilization rate of the chip area, and reduce the cost, a stacking method will be introduced. The oxide layer-nitride layer-oxide layer (Oxide-Nitride-Oxide, ONO) capacitor of the first layer is used in a high-voltage charge pump. [0003] figure 1 It is a top view structure diagram of an ONO capacitor in the prior art. figure 2 yes figure 1 Schematic diagram of the cross-sectional structure along A1-A2. see figure 1 and figure 2 The ONO capacitor is composed of a silicon substrate 10 - a tunnel oxide (Tunnel Oxide, TO) ...

AI Technical Summary

Problems solved by technology

[0005] The invention provides a NOR flash memory device and a preparation method thereof, in order to achieve the purpose of improving the reliability of the NOR flash memory device, and solve the problem of leakage or breakdown of the NOR flash memory device caused by the thin floating gate layer

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