CUDA thread placement optimization method

Abstract

The invention discloses a CUDA thread placement optimization method, and relates to a thread optimization technology based on machine learning. The invention aims to provide a CUDA (Compute Unified Device Architecture) thread placement optimization method so as to achieve the purposes of reducing the working difficulty of programming personnel and shortening the acquisition time of training data.The technical key points are as follows: program information acquisition, program information processing and machine learning model training. The program information processing comprises the steps ofperforming information summarization, numeralization processing and normalization processing on static information and program runtime information to obtain training set program features, and settinga label by utilizing a program execution time information set so as to complete the generation of label data; taking the training set program features and the label data as input, and performing performance modeling by using a support vector machine algorithm to obtain a program performance prediction model. When the thread is optimally placed in the application, the program information acquisition module needs to be called to acquire the program information of the program to be optimized. After that, the trained program performance prediction model is input, so that a proper thread block setting scheme can be obtained.

Description

technical field [0001] The invention relates to a CUDA thread placement optimization method, and relates to a machine learning-based thread optimization technology. Background technique [0002] GPUs are common hardware in modern computers, and they mainly provide basic image operations for the CPU. In recent years, based on powerful data parallel processing and floating-point computing capabilities, GPUs have been widely used in engineering applications and scientific computing fields. However, GPU has a complex structure and a multi-threaded programming model completely different from CPU, which makes it relatively complicated to develop efficient parallel programs on GPU. Therefore, it is particularly important to reduce the complexity of GPU programming and improve program performance. In 2007, NVIDIA Corporation released the program model and development environment for parallel computing under the GPU - the Unified Computing Architecture CUDA. Relying on the C langua...

AI Technical Summary

Problems solved by technology

It is not easy to set the thread block size reasonably, and a single evaluation criterion or a relatively simple strategy is only applicable to some programs

In most cases, setting larger thread blocks can improve GPU utilization, and the program concurrency will be better, but too large thread blocks may also cause GPU resource allocation conflicts and reduce program performance. Therefore, only GPU Utilization is an incomplete measure of performance

In addition, some programs are sensitive to changes in thread block size, and small-scale changes will cause large fluctuations in program performance. This shows that the factors that affect program performance are intertwined in many ways, which also makes the strategy of setting thread block size more complicated.

If you do not use the method of automatically searching for the optimal configuration but manually find the optimal configuration, you need programmers to have certain experience and adapt to the hardware environment. Performance information is collected by continuously modifying the thread block size and running the program repeatedly. The process is time-consuming. Larger, and empirical settings often fail to achieve optimal

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