SoC chip deep sleep wake-up device

Abstract

The invention discloses an SoC chip deep sleep wake-up device which comprises: a sleep wake-up module used for accessing an external wake-up signal, generating an internal wake-up signal according tothe external wake-up signal, and generating a source clock enable signal when the internal wake-up signal meets a preset wake-up requirement; a clock generation module which is used for generating a source clock signal according to the source clock enable signal; a clock stabilizing module which is used for carrying out accumulation counting on the source clock signal and generating a stable clocksignal after an accumulation counting value reaches a preset threshold value; and a clock frequency division and control module which is used for carrying out frequency division processing on the stable clock signal and then generating a plurality of clock signals capable of being used for working of an internal function module of the SoC chip. A two-stage awakening mechanism is adopted, clock signals do not need to participate in the dormancy awakening process, mistaken awakening can be avoided, and power consumption of a clock network can be avoided during dormancy.

Description

technical field [0001] The present invention relates to a SoC chip dormancy wake-up method, in particular to a SoC chip deep sleep wake-up device and method. Background technique [0002] One or more SoC (System on Chip, System on Chip) chips are usually integrated in a mobile electronic terminal. Due to the limited capacity of the battery, in order to increase the usage time of the mobile electronic terminal, the low power consumption control of the SoC chip has higher and higher requirements. [0003] For a typical structure of a SoC chip in the prior art, please refer to figure 1 , including the analog circuit part and the digital circuit part. The analog circuit part includes power generation module, clock generation module, analog signal detection module, and analog signal processing module, and the digital circuit part includes clock frequency division and control module, MCU, hardware acceleration module, storage module and interface module. One of the SoC sleep wa...

AI Technical Summary

Problems solved by technology

In the SoC chip, the clock tree network is often one of the largest sources of power consumption. Whether it is MCU sleep wake-up, or fingerprint / touch detection wake-up, the clock from the clock generation module to the clock control and frequency division module in the sleep state The tree network is working, and at the same time, some detection modules and interface modules are also working, so these two kinds of sleep are shallow sleep, which can reduce some power consumption, but cannot achieve ultra-low power consumption

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