System on chip and its interface data processing method and device

Abstract

The invention discloses a system-on-chip and an interface data processing method and device thereof, and the interface data processing method of the system-on-chip comprises the steps: obtaining an interface data processing signal comprising state information and data information, and determining a working state type corresponding to the interface data processing signal according to the state information; when the working state type is a downloading state, decoding the data information to obtain downloading data and a module type; wherein the module types comprise an MCU module type corresponding to the MCU kernel and an FPGA module type corresponding to the FPGA kernel; and writing the downloaded data into a memory of the MCU kernel or a memory of the FPGA kernel corresponding to the module type. Automatic switching of downloading or debugging modes of the MCU core and the FPGA core is achieved, port resources of the system-on-chip are saved, operation is easy and convenient, and programming errors, caused by selection errors or mode selection errors of the MCU core and the FPGA core, of the system-on-chip are avoided.

Description

technical field [0001] The invention relates to semiconductor chip technology, in particular to an on-chip system and its interface data processing method and device. Background technique [0002] At present, as the semiconductor industry enters the era of ultra-deep submicron and even nanometer processing, it is an inevitable development trend to realize a complex electronic system on a single integrated circuit chip. SoC (System on Chip, system on chip) is becoming more and more widely used. application, and the JTAG (Joint Test Action Group, joint test behavior organization) interface is an indispensable part in the system-on-chip. In the prior art, the system-on-chip includes an MCU (Microcontroller Unit, single-chip microcomputer) core and an FPGA ( Field-Programmable Gate Array, Field Programmable Gate Array) core, and both MCU core and FPGA core will reserve JTAG interface separately, such as Figure 9 As shown, the system-on-chip is connected to external computer equ...

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Problems solved by technology

[0002] At present, as the semiconductor industry enters the era of ultra-deep submicron and even nanometer processing, it is an inevitable development trend to realize a complex electronic system on a single integrated circuit chip. SoC (System on Chip, system on chip) is becoming more and more widely used. application, and the JTAG (Joint Test Action Group, joint test behavior organization) interface is an indispensable part in the system-on-chip. In the prior art, the system-on-chip includes an MCU (Microcontroller Unit, single-chip microcomputer) core and an FPGA ( Field-Programmable Gate Array, Field Programmable Gate Array) core, and the MCU core and FPGA core will separately reserve the JTAG interface, such as Figure 9 As shown, the system-on-chip is connected to external computer equipment through the two reserved JTAG interfaces, and the computer equipment can only be programmed and downloaded to the JTAG interface of the MCU core through the MCU compiler and debugger. The data in the debug mode, and the computer equipment can only be accurately connected to the JTAG interface of the FPGA core of the system-on-chip through the FPGA compiler and debugger to burn and write the data in the download mode or the data in the debug mode. The disadvantages of this solution are: First of all, the two JTAG interfaces reserved by the system on chip will occupy the port resources of the system on chip, resulting in a waste of port resources of the system on chip; at the same time, due to the need to manually select different interfaces corresponding to the MCU core and the FPGA core according to different data , and both the MCU core and the FPGA core have a download mode and a debug mode, so it is also necessary to manually select different modes. The process is cumbersome, inconvenient to operate, and error-prone. If the interface or mode selection is wrong, it will cause programming errors in the system on chip.

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