Unlock instant, AI-driven research and patent intelligence for your innovation.

Preparation method used for silicon carbide MOSFET device and capable of realizing p+ region self-alignment process

A self-alignment process, a technology of silicon carbide, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that the channel size cannot be precisely controlled, and the alignment deviation of the p+ region is not considered. Achieve the effects of reducing one-time photolithography, improving uniformity and long-term reliability, and simplifying the process

Pending Publication Date: 2019-11-19
深圳爱仕特科技有限公司
View PDF0 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, during the thermal oxidation process of polysilicon, the side moves to achieve self-aligned implantation in the source region and form a self-aligned channel. This method has strict requirements on the thermal oxidation process of polysilicon, and the size of the formed channel cannot be precisely controlled. Misalignment issues to the p+ region

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation method used for silicon carbide MOSFET device and capable of realizing p+ region self-alignment process
  • Preparation method used for silicon carbide MOSFET device and capable of realizing p+ region self-alignment process
  • Preparation method used for silicon carbide MOSFET device and capable of realizing p+ region self-alignment process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The specific embodiments described here are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0036] The present invention provides such Figure 2-17 A method for preparing a silicon carbide MOSFET device with a p+ region self-alignment process includes the following steps:

[0037] A method for preparing a silicon carbide MOSFET device with a p+ region self-alignment process, comprising the steps of:

[0038] S1, such as figu...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a preparation method used for a silicon carbide MOSFET device and capable of realizing a p+ region self-alignment process. According to the preparation method of the invention,the first ion implantation mask layer of p-wells is subjected to photoetching; and ion implantation is performed on the p-wells, so that p-well regions can be formed; after the ion implantation of the p-wells, a second ion implantation mask layer for source contact n+ regions is deposited; the second ion implantation mask layer is not subjected to photoetching, but directly subjected to etching,so that n+ ion implantation regions can be formed; ion implantation is performed, so that source contact n+ regions are formed; after the source contact n+ regions are formed, a third ion implantationmask layer for source contact p+ regions is deposited; the third ion implantation mask layer is not subjected to photoetching, but directly subjected to etching, so that p+ ion implantation regions are formed; ion implantation is performed, so that the source contact p+ regions are formed; and therefore, the self-alignment process of channel regions is achieved, at the same time, the self-alignment process of the p+ regions is achieved; primary photoetching is reduced; a process is simplified; manufacturing cost is decreased; and the uniformity and long-term reliability of the on resistance of the silicon carbide MOSFET device are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for preparing a silicon carbide MOSFET device with a p+ region self-alignment process. Background technique [0002] Silicon carbide material has excellent physical and electrical properties. With its unique advantages such as wide band gap, high thermal conductivity, large saturation drift velocity and high critical breakdown electric field, it has become a high-power, high-frequency, high-voltage It is an ideal semiconductor material for high temperature resistant and radiation resistant devices, and has broad application prospects in military and civil affairs. Silicon carbide MOSFET devices have the advantages of fast switching speed and small on-resistance, and can achieve a high breakdown voltage level at a small drift layer thickness, reduce the volume of the power switch module, and reduce energy consumption. , Converters and other application...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/16H01L29/45H01L21/336H01L29/78
CPCH01L29/78H01L29/665H01L29/45H01L29/1608
Inventor 姚金才陈宇朱超群
Owner 深圳爱仕特科技有限公司