Preparation method used for silicon carbide MOSFET device and capable of realizing p+ region self-alignment process
A self-alignment process, a technology of silicon carbide, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems that the channel size cannot be precisely controlled, and the alignment deviation of the p+ region is not considered. Achieve the effects of reducing one-time photolithography, improving uniformity and long-term reliability, and simplifying the process
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[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The specific embodiments described here are only used to explain the present invention, not to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0036] The present invention provides such Figure 2-17 A method for preparing a silicon carbide MOSFET device with a p+ region self-alignment process includes the following steps:
[0037] A method for preparing a silicon carbide MOSFET device with a p+ region self-alignment process, comprising the steps of:
[0038] S1, such as figu...
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