A three-terminal superlattice memory-computing integrated device with adjustable threshold voltage and its preparation method
A threshold voltage, superlattice technology, applied in the field of three-terminal superlattice storage and computing integrated device and its preparation, can solve the problem of limiting computer data processing speed, limited data line transmission signal rate, high energy consumption of central processing unit and memory And other issues
Active Publication Date: 2020-12-11
HUAZHONG UNIV OF SCI & TECH
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Problems solved by technology
This von Neumann structure will not only cause extremely high energy loss caused by frequent data exchange between the central processing unit and the memory, but also greatly limit the speed of computer data processing due to the limited rate of data line transmission signals.
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preparation example Construction
[0058] This embodiment also provides a method for preparing the above-mentioned three-terminal superlattice memory-computing integrated device with adjustable threshold voltage, including the following steps:
[0059] S1: Provide a substrate layer, on which the lower electrode layer and the first inverse piezoelectric layer are sequentially deposited; the substrate layer includes a silicon wafer and a thermal growth layer deposited on the silicon wafer, and the lower electrode layer is sequentially deposited on the thermal growth layer , the first inverse piezoelectric layer;
[0060] S2: Open a first through hole, the first through hole penetrates through the first reverse piezoelectric layer and contacts the surface of the lower electrode layer, and fills the heating layer inside the first through hole; the shape of the first through hole is not limited, and its cross section can be It is a circle, a square or other regular polygons, and this embodiment is preferably a circl...
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Abstract
The invention discloses a three-terminal superlattice memory-computing integrated device with adjustable threshold voltage and a preparation method thereof, which comprises a substrate layer, a lower electrode layer, a superlattice film, and an upper electrode layer; Piezoelectric layer; the first inverse piezoelectric layer is formed between the lower electrode layer and the superlattice film, and is partially filled with a heating layer for connecting the lower electrode layer and the superlattice film; the second inverse piezoelectric layer is formed Between the superlattice film and the upper electrode layer, the upper electrode layer has a raised structure that runs through the second inverse piezoelectric layer and contacts the surface of the superlattice film; the lattice constants of the first and second inverse piezoelectric layer materials can be Increase in response to external applied voltage, produce in-plane tensile stress to the superlattice film in contact with it, so that the superlattice film can adjust the threshold voltage in the phase transition process under the action of in-plane tensile stress; the present invention will calculate And the storage process is integrated into the same phase change memory to realize the integration of storage and calculation, which is conducive to reducing the power consumption of existing computers and improving the data processing speed.
Description
technical field [0001] The invention belongs to the technical field of microelectronic devices, and more specifically relates to a three-terminal superlattice memory-computing integrated device with adjustable threshold voltage and a preparation method thereof. Background technique [0002] At present, the development of various artificial intelligence technologies is in the ascendant, especially the research on brain-like devices. The characteristic of brain-like devices is that storage and calculation are implemented in the same device, that is, storage and calculation are integrated. At present, most computers use the von Neumann architecture, that is, the central processing unit and storage are separated, and the two are connected through data lines. This von Neumann structure will not only lead to extremely high energy loss caused by frequent data exchange between the central processing unit and the memory, but also greatly limit the speed of computer data processing d...
Claims
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IPC IPC(8): H01L45/00
CPCH10N70/253H10N70/801H10N70/8613H10N70/011Y02D10/00
Inventor 程晓敏冯金龙缪向水
Owner HUAZHONG UNIV OF SCI & TECH