Adaptive electric leakage compensation circuit for of LDO (low dropout regulator)

Abstract

The invention discloses an adaptive electric leakage compensation circuit for an LDO (low dropout regulator). The grid electrode of the power supply PMOS transistor MPP of the LDO is connected with the output of an error amplifier EA. The circuit is characterized in that the circuit is connected between the source electrode and drain electrode of the MPP; a sampling PMOS transistor MPS and a pairof NMOS transistors are connected so as to form the circuit; the grid electrode of the MPS and the common source electrode of the MPP and the MPS are connected with input VIN; the common drain electrode of the MPP and the MN2 is output VOUT; the common drain electrode of the MPS and the MN1 is connected with the common grid electrode of the MN1 and the MN2; the common-source of the two NMOS transistors is grounded; the size ratio of the MPS to MPP is 1:K1; the size ratio of the MN1 to MN2 is 1:K2; and K2 is greater than K1. The adaptive compensation circuit is simple in structure and practical; generated leakage current is tracked adaptively through the sampling PMOS transistor; the leakage current is completely pulled out through the two connected NMOS transistors; the output stability ofthe LDO in a temperature conversion environment can be guaranteed; and no quiescent current is generated in the circuit at the normal temperature, so that the optimization of design parameters is facilitated.

Description

technical field [0001] The invention relates to a circuit design for optimizing the performance of an LDO, in particular to a circuit for the LDO to perform self-adaptive leakage compensation for temperature fluctuations. Background technique [0002] LDO is a low dropout regulator, which is a low-dropout linear regulator, which is relative to the traditional linear regulator. Traditional linear regulators, such as 78XX series chips, require the input voltage to be at least 2V~3V higher than the output voltage, otherwise they cannot work normally. But in some cases, such conditions are obviously too harsh, such as 5V to 3.3V, the voltage difference between input and output is only 1.7v, which obviously does not meet the working conditions of traditional linear regulators. In response to this situation, chip manufacturers have developed LDO-type voltage conversion chips. [0003] An LDO is a linear regulator that uses a transistor or field effect transistor (FET) operating ...

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Problems solved by technology

[0004] However, for an LDO with a positive output voltage, when the operating environment heats up, its power supply MOS tube (that is, POWER MOS) will generate a proportionally increased leakage current. If the load current in the LDO operating state is less than the leakage current, the output of the LDO will The performance will be greatly reduced, and there will be abnormal

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