Semiconductor device, method for manufacturing same, and mask plate

Abstract

The invention provides a semiconductor device, a method for manufacturing the same, and a mask plate. In the method for manufacturing the semiconductor device, after a patterned core layer having cores in both a gate dense region and a gate sparse region is formed, a spacer is formed on the sidewalls of the cores. Thus, when a gate layer is etched by using the spacer as a mask, an etching load effect between the gate dense region and the gate sparse region can be reduced or even completely avoided, so as to improve the uniformity of the key dimensions of a finally formed first gate and ensurethe shape of an edge first gate. Further, after the gate layer is etched by using the spacer as the mask, the bottom of the gate layer is kept connected, and a protective layer protects the gate layerin a corresponding region of a second gate in the gate sparse region so as to further etching the gate layer to form the first gate in the gate dense region and the second gate in the gate sparse region. Each of the second gates has a base structure and a plurality of separate discrete structures on the base structure.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device, a manufacturing method thereof, and a mask plate. Background technique [0002] At present, with the rapid development of ultra-large-scale integrated circuits, the integration of chips is getting higher and higher, and the circuit design size is getting smaller and smaller. The various effects caused by the high density and small size of devices have an increasing impact on the semiconductor manufacturing results. It is outstanding that, especially in the process below the 28nm technology node, the change of the critical dimension (CD, Critical Dimension) of the circuit has more and more influence on the performance of the device. [0003] As we all know, since the gate usually has the smallest physical size in the semiconductor manufacturing process, and the width of the gate is usually the most important critical dimension on th...

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Problems solved by technology

[0004] In practice, it has been found that when the gates of the dense region and the sparse region are formed in the same etching process, there is an etching difference (I / D loading, or called sparse / dense loading effect), affected by the I / D loading, the gates at the edge of the dense area tend to have abnormal contours and depths, and the abnormal edge gates will affect the middle of the dense area. Both the gate and the gate of the sparse region are adversely affected, which in turn affects the performance of the device

For example, in a NAND flash memory, the distribution density of the select gate (select gate, SG, that is, a sparse gate) and the word line (wordline, WL, corresponding to a control gate, that is, a dense gate) are different, and the select gate The distance between its nearest neighbor word line is greater than the distance between two adjacent word lines. As the critical size of NAND flash memory shrinks day by day, there will be increasingly serious etching load between word line and select gate. effect, which makes the CD uniformity of the word line worse, and multiple word lines on the edge (that is, multiple word lines close to the select gate) often produce abnormalities in profile and depth, which in turn affects the performance of the device

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