Unlock instant, AI-driven research and patent intelligence for your innovation.

Clock generator circuit and clock generation method

A clock generation circuit and clock generator technology, applied to electrical components, amplifiers with semiconductor devices/discharge tubes, automatic power control, etc., can solve problems that affect loop performance, loop instability, and failure to operate

Active Publication Date: 2019-12-13
M31 TECH
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, when the integrated circuit is in production and operation, it will face the problem of the variation of three PVT parameters such as process (Process), voltage (Voltage) and temperature (Temperature), which will cause the loop bandwidth to affect the loop performance due to the drift. , even beyond the allowable range, making the loop unstable and unable to operate

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Clock generator circuit and clock generation method
  • Clock generator circuit and clock generation method
  • Clock generator circuit and clock generation method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0036] see figure 1 , is the first embodiment of the clock generating circuit 100 of the present invention, including a charge pump (ChargePump; CP) unit 1, a low-pass filter (Low-Pass Filter; LPF) unit 2, a voltage-to-current conversion unit (V-I Converter) 3, and a current-controlled clock generator. Here, the current-controlled clock generator is illustrated by taking a current-controlled oscillator (Current Controlled Oscillator; CCO) 4 as an example, wherein the charge pump unit 1 can be coupled to a phase detector Detector (Phase Detector; PD) 6, and the current-controlled oscillator 4 can be coupled to a frequency divider circuit (Frequency Divider) 5, thereby forming a phase-locked loop (PLL).

[0037] The frequency dividing circuit 5 receives an output clock signal F OUT , and generate a frequency-divided clock signal F FBK , and the output clock signal F OUT The frequency is divided by the frequency-divided clock signal F FBK The frequency of is equal to a predet...

no. 2 example

[0054] see figure 1 and image 3 , is the second embodiment of the present invention, derived from the first embodiment, wherein the voltage-to-current conversion unit 3 includes a first voltage-to-current converter 32, which includes a first operational amplifier (Operational Amplifier; OP) 321 and a second resistive element K VI1 .

[0055] The first operational amplifier 321 includes a positive input terminal, a negative input terminal, and an output terminal coupled to the negative input terminal, and is also coupled to the first charge pump 11 of the charge pump unit 1 . The first operational amplifier 321 is used as a single-gain buffer, and is coupled to the first filter 21 of the low-pass filter unit 2 through the positive input terminal to receive the first control voltage V C1 , and through its output coupled to the second resistive element K VI1 to generate the control current I CCO , and generate the first reference current I for the charge pump unit 1 to receiv...

no. 3 example

[0060] see figure 1 and Figure 5 , Figure 5 It is the third embodiment of the present invention, which is derived from the second embodiment. In this embodiment, the first filter 21 of the low-pass filter unit 2 and the first filter 21 of the voltage-to-current conversion unit 3 The voltage-to-current converter 33 shares the same operational amplifier, that is, the first operational amplifier 331 , and its design is the same as that of the first operational amplifier 321 in the second embodiment. Although the present embodiment discloses sharing the same operational amplifier, the first filter 21 and the first voltage-to-current converter 33 can also use different operational amplifiers respectively, and its design method is the same as that of the first operational amplifier of the present embodiment. Amplifier 321 is the same.

[0061] The first operational amplifier 331 includes a positive input terminal receiving a reference voltage and a positive input terminal coupl...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a clock generator circuit and a clock generation method. The clock generator circuit includes a charge pump unit, a low-pass filter unit, a current-controlled clock generator and a voltage-to-current converter unit. The charge pump unit provides a pump current at an output terminal thereof. The low-pass filter unit is coupled to the output terminal of the charge pumpunit, and develops a control voltage at an output terminal thereof based on the pump current. The voltage-to-current converter unit is coupled to the output terminal of the low-pass filter unit, thecurrent-controlled clock generator and the charge pump unit, and provides a control current to the current-controlled clock generator. Each of the low-pass filter unit and the voltage-to-current converter unit includes a resistive element.

Description

technical field [0001] The present invention relates to a clock generation circuit and method, in particular to a clock generation circuit and a clock generation method with loop bandwidth not affected by process, voltage and temperature (PVT for short). Background technique [0002] Phase-Locked Loop (PLL), Frequency-Locked Loop (FLL), Clock and Data Recovery Circuit (CDR), or Delay-Locked Loop (DLL) Such clock generators have been widely used in the design of integrated circuits in various fields. When designing the above-mentioned clock generator, the loop bandwidth (Loop Bandwidth) is an important design parameter. The loop bandwidth will affect various performances of the loop, such as stability, locking speed, noise, etc. Usually, the loop The bandwidth is designed between one tenth and one hundredth of the frequency of the input clock signal. Therefore, in each different application specification, the designer must redesign the loop parameters to meet the loop bandw...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03L7/08H03L7/089
CPCH03L7/0891H03L7/093H03L7/099H03L7/0893H03L7/18H03L2207/06H03F3/45188H03F2200/129H03F2200/144H03F2200/165H03F2203/45116H03F2203/45512H03F2203/45526H03H7/06H03L7/0807H03L7/087H03L7/0895
Inventor 吴旻庭
Owner M31 TECH