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Low emi deep trench isolation trench type power semiconductor device and manufacturing method thereof

A power semiconductor, deep trench isolation technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as EMI interference, high cost, large area, etc., to reduce chip cost, Improvement of chip current density and reduction of EMI interference

Active Publication Date: 2021-03-23
江苏芯长征微电子集团股份有限公司 +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] To sum up, it can be seen that the gate and source of existing power semiconductor devices are located on the front side at the same time, and the drain or collector is located on the back side. Since the drain or collector is welded on the packaging substrate during packaging, and the drain is at a high potential, Therefore, the drain or collector of the power semiconductor device is equivalent to the antenna effect, which will radiate the electromagnetic field outward, causing EMI interference
In addition, power semiconductor devices pursue high frequency and high current density, but due to the existence of parasitic inductance and capacitance, too high switching frequency will cause serious EMI interference
[0013] At the same time, since the terminal structure of power semiconductor devices currently adopts a combination of field limiting rings and field plates, in order to achieve a high breakdown voltage, multiple field limiting rings are required, and multiple rings will occupy a relatively large area. Thus limiting the increase in current density, the cost is relatively high

Method used

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  • Low emi deep trench isolation trench type power semiconductor device and manufacturing method thereof
  • Low emi deep trench isolation trench type power semiconductor device and manufacturing method thereof
  • Low emi deep trench isolation trench type power semiconductor device and manufacturing method thereof

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Embodiment Construction

[0069] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0070] In order to effectively reduce EMI interference, reduce chip area, reduce cost, and increase current density, taking an N-type power semiconductor device as an example, the present invention includes a semiconductor substrate 1 with an N conductivity type, and at the center of the semiconductor substrate 1 The cell area and the terminal area located at the outer circle of the cell area are set in the area; the source metal 15 for connecting the cells in the cell area in parallel is arranged on the front side of the semiconductor substrate 1, and the semiconductor substrate 1 A back electrode structure is set on the back;

[0071]On the cross-section of the power semiconductor device, a P-type base region 11 penetrating through the semiconductor substrate 1 is provided in the upper part of the semiconductor substrate 1, and a plurality of terminal via hol...

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Abstract

The present invention relates to the technical field of power semiconductor devices, and relates to a power semiconductor device and a preparation method therefor, and particularly, a low-EMI deep trench isolation trench type power semiconductor device and a preparation method therefor. In the present invention, terminal through hole isolation is used for replacing an existing field limiting ring terminal structure, so that the terminal area is remarkably reduced, the chip costs are reduced, and the chip current density is improved. A gate metal and a back electrode structure are placed on the back surface of a semiconductor substrate, and a source metal is located on the front surface of the semiconductor substrate; during package, the source metal is welded on the package substrate, and the gate metal and the drain metal are led out by means of routing. Because the source metal is at a low potential, a point location of the package substrate is kept at a low potential, the effect of the package substrate emitting an electromagnetic field outwards is basically eliminated, and the EMI interference is reduced.

Description

technical field [0001] The invention relates to a power semiconductor device and a preparation method thereof, in particular to a low EMI deep trench isolation trench type power semiconductor device and a preparation method thereof, belonging to the technical field of power semiconductor devices. Background technique [0002] Power semiconductor devices operate at relatively high voltage and current, are used for energy conversion and transmission, and are generally used as switching devices. MOSFET is a field-effect unipolar conductive power semiconductor device that controls the on and off between the source and drain through the gate. The IGBT is a bipolar conductive power semiconductor device that controls the conduction of the collector and the emitter through the gate. The main difference from N-type MOSFET devices is that there is P-type doping implantation on the back of N-type IGBT devices, and other structures are basically the same. [0003] EMI interference is ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/552H01L29/78H01L29/739H01L29/06H01L21/336H01L21/331
CPCH01L23/552H01L29/0696H01L29/66333H01L29/66712H01L29/7398H01L29/7802
Inventor 白玉明杨飞吴凯张广银朱阳军
Owner 江苏芯长征微电子集团股份有限公司
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