Burr-free asynchronous set TSPC type D trigger with scanning structure

Abstract

The invention discloses a burr-free asynchronous set TSPC type D trigger with a scanning structure. The circuit comprises an enable circuit, a first-stage inverting logic, a second-stage inverting logic, a third-stage inverting logic and a fourth-stage inverting logic, wherein the first-stage inverting logic is provided with an input end of an enable circuit, a scanning signal SI, input data D, asetting signal S, an input end of a clock CP and an output end of a signal ml_a, wherein the second-stage inverting logic is used for generating a signal s1_b from a signal ml_a under the control of aclock CP, the third-stage inverting logic is used for generating a signal s1_a from a signal s1_b under the control of the clock CP and a setting signal S, and the fourth-stage inverting logic is used for inverting the signal s1_a and then outputting a signal Q. According to the invention, the burr problem and the power consumption loss can be effectively overcome, the high working speed and thesmall area can be maintained, the general adaptability can be improved, and the method can be suitable for various high-performance microprocessor designs.

Description

technical field [0001] The invention relates to a high-speed master-slave D flip-flop of high-performance integrated circuit design technology, in particular to a burr-free asynchronous setting TSPC (True Single Phase Clock, true single-phase clock) type D flip-flop with scanning structure. Background technique [0002] Since the advent of CMOS integrated circuit technology, flip-flops have always been one of the core components of digital integrated circuits. They are the basic units for implementing sequential logic such as pipelines, state machines, counters, and register files. Their speed directly affects the performance of circuits and chips. There are many types of D flip-flops, which are divided into RS flip-flops, JK flip-flops, D flip-flops, T flip-flops and other functional types; according to different circuit structures, they are divided into master-slave structure, sensitive amplifier structure and maintaining blocking structure etc. Among them, the D flip-flo...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a burr-free asynchronously set TSPC type D flip-flop with a scan structure in view of the problems of glitches and power consumption in the current traditional TSPC-type D flip-flop and the existing improvements are not perfect. The invention can effectively overcome the glitch problem and its power consumption loss, maintain a high working speed and a small area, and improve its general adaptability, which can be adapted to various high-performance microprocessor designs

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