12T TFET SRAM unit circuit structure with high stability

Abstract

The invention discloses a 12T TFET SRAM unit circuit structure with high stability. The circuit structure comprises ten NTFET transistors and two PTFET transistors, the ten NTFET transistors are sequentially recorded as N1 to N10, the two PTFET transistors are respectively recorded as P1 and P2, and a power supply VDD is electrically connected with drains of an NTFET transistor N7 and an NTFET transistor N8; and the drain electrode of the PTFET transistor P1 is electrically connected with the drain electrode of the NTFET transistor N1, the grid electrode of the NTFET transistor N2, the grid electrode of the NTFET transistor N4, the drain electrode of the NTFET transistor N5, the grid electrode of the NTFET transistor N7 and the grid electrode of the PTFET transistor P2. According to the circuit structure, under the condition that an external read-write control circuit is not changed, the read, write and hold capacities of a traditional TFET SRAM unit structure are improved, and the stability of the SRAM unit is improved.

Description

Technical field [0001] The present invention relates to the technical field of integrated circuit design, in particular to a 12T TFETSRAM unit circuit structure with high stability. Background technique [0002] With the development of mobile electronic products, people's demand for low power consumption of integrated circuits has become more and more urgent. In recent years, MOSFET (metal-oxide semiconductor field effect crystal) has become an important component of digital integrated circuits and analog integrated circuits. section. However, with the development of integrated circuit technology nodes, some shortcomings of MOSFETs in ultra-low power circuits make it difficult to obtain satisfactory results. In MOSFET, the continuously decreasing power supply voltage causes the delay of SRAM (Static Random Access Memory) to increase exponentially; reducing the threshold voltage (VT) of the MOSFET device to maintain a reasonable drive current under low power supply voltage will i...

AI Technical Summary

Problems solved by technology

When a forward bias voltage is applied to the TFET, there will always be a forward bias leakage current that is not controlled by the gate voltage, which makes the TFET a forward bias leakage current in the hold state when the TFET is used as a SRAM transmission tube. Thus affecting the stability of storage nodes

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